Lsi Logic Corporation

Sudhir K Patel

Richard D Blinne

A method determines the behavior of a logic cell that receives input signals resulting in a narrow pulse or 'glitch.' If the pulse width of the output pulse is narrower than a pulse rejection period, the output pulse is rejected and is not propagated to subsequent logic cells connected to the output. The method employs a first internal logic cell model which is assigned an inertial delay function, and a second internal logic cell model which is assigned a transport delay function. In combination, the first and second logic cell models result in an effective propagation delay value, subject to the pulse rejection feature. An exemplary VHDL model is disclosed. A program product embodies a logic cell model in VHDL providing pulse rejection capabilities for output pulses with pulse width smaller than a pulse rejection period.

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Fort Collins, CO, United States of America

Sudhir K Patel