Intel Corporation

Suddhasattwa Nad

Jeremy D Ecton

Aleksandar Aleksov

Rahul N Manepalli

Brandon C Marin

Marcel Arlan Wall

Srinivas V Pietambaram

Darko Grujicic

Adel A Elsherbini

Feras Eid

Kristof Darmawikarta

Mathew J Manusharow

Krishna Bharath

Leonel R Arana

Javier Soto Gonzalez

Meizi Jiao

Oscar Ojeda

Rengarajan Shanmugam

Yonggang Li

Hsin-Wei Wang

Telesphor Kamgaing

Robert L Sankman

Ravindranath Vithal Mahajan

William J Lambert

Mihir K Roy

Gang Duan

Tarek A Ibrahim

Brandon M Rawlings

Nicholas S Haehn

Yidnekachew S Mekonnen

Xiaoying Guo

Benjamin Duong

Matthew L Tingey

Sashi S Kandanur

Arnab Roy

Haobo Chen

Jieying Kong

Roy Dittler

Bohan Shan

Timothy White

Mohammad Mamunur Rahman

Georgios C Dogiamis

Omkar G Karhade

Robert Alan May

Zhiguo Qian

Veronica Aleman Strong

Hiroki Tanaka

Thomas L Sounart

Dingying David Xu

Xavier Francois Brun

Sri Chaitra Jyotsna Chavali

Bai Nie

Ravindra V Tanikella

Jason M Gamba

Hongxia Feng

Vahidreza Parichehreh

Sandeep Gaan

Sarah Blythe

Xiaoxuan Sun

Marcel A Wall

Wei Wei

Ala Omer

Adrian Bayraktaroglu

Christy Sennavongsa

Ao Wang

Helme A Castro De La Torre

Yi Yang

Thomas I Sounart

Ke Liu

Yiyang Zhou

Jason Steill

Helme Castro De La Torre

Substrate assemblies having adhesion promotor layers and related methods are disclosed. An example apparatus includes a substrate, a dielectric layer, a first copper layer between the substrate and the dielectric layer, and a film between the dielectric layer and the first copper layer. The film including silicon and nitrogen and being substantially free of hydrogen. A via in the dielectric layer is to provide access to the first copper layer. A portion of the first copper layer uncovered in the via, a wall of the via and the portion of the first copper layer to be substantially free of fluorine. A seed copper layer positioned on the dielectric layer. The via wall and the portion of the first copper layer. The seed copper layer and the first copper layer define an undercut at an interface between the seed copper layer and the first copper layer.

Substrates having adhesion promotor layers and related methods

Glass substrates having transverse capacitors for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a glass substrate having a through glass via between a first surface and a second surface opposite the first surface. A transverse capacitor is located in the through glass via. The transverse capacitor includes a dielectric material positioned in a first portion of the through glass via, a first barrier/seed layer positioned in a second portion of the through glass via, and a first conductive material positioned in a third portion of the through glass via.

Glass substrates having transverse capacitors for use with semiconductor packages and related methods

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

Microelectronic assemblies including interconnects with different solder materials

Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

Capacitors in through glass vias

An electronic substrate may be fabricated having at least two glass layers separated by an etch stop layer, wherein a bridge is embedded within one of the glass layers. The depth of a cavity formed for embedding the bridge is control by the thickness of the glass layer rather than by controlling the etching process used to form the cavity, which allows for greater precision in the fabrication of the electronic substrate. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.

Electronic substrate having an embedded etch stop to control cavity depth in glass layers therein

An electronic substrate may be fabricated having a dielectric material, metal pads embedded in the dielectric material with co-planar surfaces spaced less than one tenth millimeter from each other, and a metal trace embedded in the dielectric material and attached between the metal pads, wherein a surface of the metal trace is non-co-planar with the co-planar surfaces of the metal pads at a height of less than one millimeter, and wherein sides of the metal trace are angled relative to the co-planar surfaces of the metal pads. In an embodiment of the present description, an embedded angled inductor may be formed that includes the metal trace. In an embodiment, an integrated circuit package may be formed with the electronic substrate, wherein at least one integrated circuit devices may be attached to the electronic substrate. Other embodiments are disclosed and claimed.

Angled inductor with small form factor

An electronic substrate may be formed having at least one metal-to-dielectric adhesion promotion material layer therein. The electronic substrate may comprise a conductive metal trace, a dielectric material layer on the conductive metal trace, and the adhesion promotion material layer between the conductive metal trace and the dielectric material layer, wherein the adhesion promotion material layer comprises an organic adhesion material and a metal constituent dispersed within the organic adhesion material, wherein a metal within the metal constituent has a standard reduction potential greater than a standard reduction potential of the conductive metal trace.

Dielectric-to-metal adhesion promotion material

An integrated circuit package comprising an integral structural member embedded within dielectric material and at least partially surrounding a keep-out zone of a co-planar package metallization layer. The integral structural member may increase stiffness of the package without increasing the package z-height. The structural member may comprise a plurality of intersecting elements. Individual structural elements may comprise conductive vias that are non-orthogonal to a plane of the package. An angle of intersection and thickness of the structural elements may be varied to impart more or less local or global rigidity to a package according to a particular package application. Intersecting openings may be patterned in a mask material by exposing a photosensitive material through a half-penta prism. Structural material may be plated or otherwise deposited into the intersecting openings.

Structural elements for application specific electronic device packages

An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.

Selectively roughened copper architectures for low insertion loss conductive features

Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

Conductive route patterning for electronic substrates

Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

High performance integrated RF passives using dual lithography process

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.

Subtractive etch resolution implementing a functional thin metal resist

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the second thickness is different from the first thickness. In some embodiments, the first conductive trace and the second conductive trace have rectangular cross-sections.

Microelectronic assemblies having conductive structures with different thicknesses

A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.

Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes first waveguides over a package substrate. The first waveguides include first angled conductive layers, first transmission lines, and first cavities. The semiconductor package also includes a first dielectric over the first waveguides and package substrate, second waveguides over the first dielectric and first waveguides, and a second dielectric over the second waveguides and first dielectric. The second waveguides include second angled conductive layers, second transmission lines, and second cavities. The first angled conductive layers are positioned over the first transmission lines and package substrate having a first pattern of first triangular structures. The second angled conductive layers are positioned over the second transmission lines and first dielectric having a second pattern of second triangular structures, where the second pattern is shaped as a coaxial interconnects enclosed with second triangular structures and portions of first dielectric.

Method for fabricating multiplexed hollow waveguides of variable type on a semiconductor package

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Chandler, AZ, United States of America

Suddhasattwa Nad