Taiwan Semiconductor Manufacturing Comp. Ltd.

Su-Yu Yeh

Keng-Ying Liao

Po-Zen Chen

Ko-Bin Kao

Li-Jen Wu

Huai-jen Tung

Chia-Hung Chung

Yen-Jou Wu

Chih Wei Sung

Yu-Kai Chen

Chi-Chung Jen

Chih-Ming Lee

Yu-Chu Lin

Ching-Chung Su

Chia-Ming Pan

Ping-Pang Hsieh

Chih-Wei Sung

Ming-Hung Lin

Zhi-You Ke

Hsin-Hui Lin

Yu-Liang Wang

Huai-Tei Yang

Chien-Chih Chen

Yu Kai Chen

Chung-Bin Tseng

Shi-Ming Wang

Mu-Han Cheng

Oliver Yu

Jih-Hwa Wang

Tzu-Shin Chen

Chao-Jie Tsai

Jun-Yang Lai

Chin-Yu Lin

H L Chen

Chung-Te Lin

Hung-Ming Chen

Cheng-Yi Huang

Hung-Chih Wang

Chun-Yu Chen

Meng-Chang Liu

Hsing-Jui Lee

Yu-Ting Tsai

Chin-Nan Wu

Chin-Te Huang

Chia-Yun Chen

Tzu-Pin Lin

Yong-Ting Wu

Jeng-Yang Pan

Hong-Ming Lo

Chien-Jiun Wang

Ta-Cheng Wei

Chou-Jie Tsai

Lu-Chang Chen

Jang-Cheng Hsieh

Meng-Shiun Shieh

Chia-Chun Wu

Tsung-Yi Yang

Chun-Hai Huang

Wen-Chieh Hsieh

Chun-Wei Chou

Po Hsun Chen

Tai-Chin Wu

Chung-I Hung

S Y Chen

Shao-Shuo Wu

Jeng Yang Pan

Forster Yuan

Hsien-Li Chen

Cheng-Yang Pan

Chi-Bing Chen

Wen-Shiung Chen

Wen-Fang Tang

The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

Polysilicon removal in word line contact region of memory devices

A method includes sequentially depositing a floating gate layer, a dielectric structure stack, and a control gate layer over a substrate. A first etching process is performed to pattern the control gate layer, the dielectric structure stack, and a top portion of the floating gate layer to form a control gate, a dielectric structure, and a top portion of a floating gate over a bottom portion of the floating gate layer. A sidewall of the top portion of the floating gate is concave. A first spacer structure is formed on the sidewall of the top portion of the floating gate, a sidewall of the dielectric structure, and a sidewall of the control gate. A second etching process is performed to pattern the bottom portion of the floating gate layer to form a bottom portion of the floating gate after forming the first spacer structure.

Memory device and manufacturing method thereof

A system and method for cleaning a preclean process chamber in between wafer processing. The internal pressure of the preclean process chamber is reduced to a first pressure and a first gas that consists of oxygen and an inert or noble gas, is introduced into the chamber. Plasma is generated within the preclean process chamber using the first gas at the first pressure. Internal pressure is then reduced to a second pressure, less than the first, and the first gas is continued into the chamber. Plasma is then generated using the first gas at the second pressure. Thereafter, a second gas, consisting of an oxygen-free inert or noble gas, is introduced into the chamber at the second pressure, following which plasma is generated within the chamber using only the second gas.

System and method for cleaning a pre-clean process chamber

A wafer treatment system is provided. The wafer treatment system includes a wafer treatment chamber defining a treatment area within which a wafer is treated. The wafer treatment system includes a gas injection system. The gas injection system includes a gas injector configured to inject a first gas, used for treatment of the wafer, into the treatment area. A first gas tube is configured to conduct the first gas at a first temperature to the gas injector. The gas injection system includes a heating enclosure enclosing the gas injector. A second gas tube is configured to conduct a heated gas to the heating enclosure to increase an enclosure temperature at the heating enclosure to a second enclosure temperature. A temperature of the first gas is increased in the gas injector from the first temperature to a second temperature due to the second enclosure temperature at the heating enclosure.

Wafer treatment system and method of treating wafer

A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.

BSI chip with backside alignment mark

A method of manufacturing a semiconductor device is as below. An exposed photoresist layer is developed using a developer supplied by a developer supplying unit. An ammonia gas by-product of the developer is discharged through a gas outlet of the developer supplying unit into a treating tool. The ammonia gas by-product is retained in the treating tool. A concentration of the ammonia gas by-product is monitored.

Manufacturing method of semiconductor device and semiconductor processing system

A method includes depositing a gate dielectric film over a substrate. A floating gate layer and a control gate layer are deposited over the gate dielectric film. The control gate layer is patterned to form a control gate over the floating gate layer. A top portion of the floating gate layer is patterned. A spacer structure is formed on a sidewall of the control gate and over a remaining portion of the floating gate layer. The remaining portion of the floating gate layer is patterned to form a bottom portion of a floating gate. A ratio of the bottom width of the bottom portion to the middle width of the bottom portion is in a range between about 103% and about 108%. The gate dielectric film is patterned form a gate dielectric layer.

In a method for forming a semiconductor device photo-sensing regions are formed over a frontside of a substrate. A first layer is formed over a backside of the substrate and is patterned to form a plurality of grid lines. The grid lines can define a plurality of first areas and a plurality of second areas. A second layer may be formed over exposed portions of the backside, the gridlines, the first areas, and the second areas and a third layer may be formed over the second layer. The second and third layer may have different etch rates and the third layer is pattern so as to remove the third layer from over the plurality of first areas.

Image sensor grid and method of manufacturing same

An image sensor structure includes a semiconductor device, a plurality of image sensing elements formed in the semiconductor substrate, an interconnect structure formed on the semiconductor substrate, and a composite grid structure over the semiconductor substrate. The composite grid structure includes a tungsten grid, an oxide grid over the tungsten grid, and an adhesion enhancement grid spacing the tungsten grid from the oxide grid.

Image sensor grid and method of fabrication of same

The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot, performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

A method of manufacturing a semiconductor device and a semiconductor processing system are provided. The method includes the following steps. A photoresist layer is formed on a substrate in a lithography tool. The photoresist layer is exposed in the lithography tool to form an exposed photoresist layer. The exposed photoresist layer is developed to form a patterned photoresist layer in the lithography tool by using a developer. An ammonia gas by-product of the developer is removed from the lithography tool.

A memory device includes a floating gate, a control gate, a spacer structure, a dielectric layer, and an erase gate. The floating gate is above a substrate. The floating gate has a curved sidewall. The control gate is above the floating gate. The spacer structure is in contact with the control gate and the floating gate. The spacer structure is spaced apart from the curved sidewall of the floating gate. The dielectric layer is in contact with the spacer structure and the curved sidewall of the floating gate. The erase gate is above the dielectric layer.

The present disclosure describes the formation of a pad structure in an image sensor device using a sacrificial isolation region and a silicon oxide based stack with no intervening nitride etch-stop layers. The image sensor device includes a semiconductor layer comprising a first horizontal surface opposite to a second horizontal surface; a metallization layer formed on the second horizontal surface of the semiconductor layer, where the metallization layer includes a dielectric layer. The image sensor device also includes a pad region traversing through the semiconductor layer from the first horizontal surface to the second horizontal surface. The pad region includes an oxide layer with no intervening nitride layers formed on the dielectric layer of the metallization layer and a pad structure in physical contact with a conductive structure of the metallization layer.

Image sensor with pad structure

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Tainan, Taiwan

Su-Yu Yeh