Taiwan Semiconductor Manufacturing Comp. Ltd.

Su-Ying Su

Chien-Hung Lin

Chi-Ming Wu

Kang-Min Kuo

Meng-Chang Liu

Jyh-Feng Lin

Wen-Hsiang Tang

Fu-Ying Chiu

Ming-Shu Yen

A process for etching back SOG during planarization is described. A mix of CHF.sub.3 and CF.sub.4 in an argon carrier gas is used, with the latter having a flow rate of about 175 SCCM. An RF discharge is initiated for about 10 seconds during which time etching occurs. The system is then cleared of all reactive gases by a brief pumpdown to base pressure. In a key feature of the invention, argon alone is now admitted to the reaction chamber at a greater than normal flow rate of about 273 SCCM. This high flow rate is maintained for about 40 seconds (including about 10 seconds to reach an equilibrium pressure of about 225 mtorr) following which the system is pumped out again and the process is terminated. If this procedure is followed, no polymeric residue is generated at the surface of any exposed titanium nitride.

Removal of SOG etchback residue by argon treatment

A method for making improved polysilicon FET gate electrodes having composite sidewall spacers is achieved. After forming the polysilicon gate electrodes on the substrate, a SiO.sub.2 stress-release layer is deposited having a trapezoidal shape. A Si.sub.3 N.sub.4 layer is deposited and plasma etched back using the SiO.sub.2 layer as an etch-endpoint-detect layer to form composite sidewall spacers that include portions of the trapezoidal-shaped oxide layer. The SiO.sub.2 layer protects the source/drain areas from plasma etch damage that could cause high leakage currents. The Si.sub.3 N.sub.4 also extends over the SiO.sub.2 layer at the upper edges of the polysilicon gate electrodes. This prevents erosion of the SiO.sub.2 along the gate electrodes when the remaining oxide is removed from the source/drain areas using hydrofluoric acid wet etching. When an insulating layer is deposited over the FETs, and self-aligned contact openings are etched to the source/drain areas and extending over the gate electrodes, the Si.sub.3 N.sub.4 extending over the portion of the trapezoidal-shaped SiO.sub.2 layer that forms part of the composite sidewall spacer protects the SiO.sub.2 from etching. This results in more reliable contacts without degrading the FET performance.

Method for making improved polysilicon FET gate electrodes having

Growing community of inventors

Taipei, Taiwan

Su-Ying Su