Advanced Semiconductor Engineering, Inc.

Industrial Technology Research Institute

Other

Su Tao

Chun-Chi Lee

Ho-Ming Tong

Jen-Kuang Fang

Jau-Shoung Chen

Ching-Huei Su

Yu-Chen Chou

Tsung-Hua Wu

Min-Lung Huang

Chao-Fu Weng

Yung-Chi Lee

Chun Hung Lin

Yu-Fang Tsai

Kun-Ching Chen

Tai-Chun Huang

Yu-Choung Chang

Jen-Chieh Kao

Po-Jen Cheng

Kuo-Chung Yee

Chih-Huang Chang

Jeng-Da Wu

Kuang-Hui Chen

William Tze-You Chen

Meng-Hui Lin

Kuo Chung Yee

Shyh-Wei Wang

Jen Chieh Kao

Chih Lung Chen

Hsing Jung Liau

Chun-Hung Lin

Shih-Chang Lee

Wei-Chung Wang

Chih-Ming Chung

Kuo-Pin Yang

Ching-Feng Lai

Kuang-Lin Lo

Kao-Yu Hsu

Shih-Kuang Chen

Tse-Liang Hsiao

Hsueh-Te Wang

Kun-I Liang

Yao-Hsin Feng

Shih Chang Lee

Chih-Cheng Yang

Chih-Lung Chen

Tao-Yu Chen

Shin Hua Chao

Jian Wen Chen

Chin-Chen Wang

Sai Man Li

Han-Hsiang Huang

Jau-Yuen Su

Hsing-Jung Liau

Jian-Cheng Chen

Yung-I Yeh

Sung-Fei Wang

Chian-Chi Lin

Shin-Hua Chao

Chun-Chung Yang

Shyh-Ing Wu

Wen-Pin Huang

Chi Tsung Chiu

Ho Ming Tong

Ching-Fu Horng

Ann Huang

Kuang-Chun Chou

Sung Mao Wu

Simon Lee

Chi-Wen Chang

Shih-Chih Chen

Chi Cheng Pan

Kuo Pin Yang

I Zeng Lee

Yire-Zine Lee

Yu-Ching Tsai

Chin-Ming Chung

Chin-Long Wu

Yire Zine Lee

Yei-Shen Wu

Tao Yu Chen

Hsin-Hsing Wei

Shwu-Er Huang

Yueh Lung Lin

Yao Hsin Feng

Sung Ching Hung

A method of manufacturing a semiconductor chip package includes mechanically and electrically connecting a semiconductor chip to a top surface of a main substrate, securely attaching the semiconductor chip to a recessed cavity on a bottom surface of an interconnection substrate, mechanically and electrically connecting the main substrate to the interconnection substrate, and cutting the main substrate to form a central substrate and a peripheral substrate wherein the semiconductor chip is disposed on the central substrate. The cutting step is conducted either (i) by forming a plurality of slots such that the central substrate and the peripheral substrate are partially conned to each other or (ii) by completely separating the central substrate and the peripheral substrate.

Semiconductor chip package

A method of wafer stacking packaging. The method comprises providing a die array including a plurality of singulated first dies cut from a first wafer; providing a second wafer with inseparate the second dies and an adhesive layer on an active surface thereof; pre-cutting the second wafer to a specified depth from the active surface thereof; stacking the active surface of second wafer onto a backside of the first dies, wherein each of the second dies only stack on one of the first dies; thinning the second wafer from the backside thereof to form a plurality of singulated the second dies stacked on the first dies simultaneously.

Wafer stacking package method

A semiconductor package comprises a semiconductor chip, a lid, a plurality of traces, a compliant layer, a plurality of conductive pastes, and a plurality of solder pads. The semiconductor chip has an active surface, a backside, and a plurality of bonding pads disposed on the active surface. The lid covers the active surface of the semiconductor chip. The traces are disposed between the lid and the active surface of the semiconductor chip, and are electrically connected to the bonding pads. The compliant layer covers the backside of the semiconductor chip for isolating the traces. The conductive pastes are electrically connected to the traces, and the solder pads are electrically connected to the conductive pastes.

Semiconductor package and method for manufacturing the same

The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

Multi-chip package structure

A process for sawing a substrate strip marks corresponding to substrate areas of substrate strips which are arranged side-by-side on a plate. A saw machine is mechanically moved to the substrate areas and positioned by the alignment marks of corresponding substrate areas for cutting the substrate areas of the substrate strips in the first phase. Then the saw machine is further mechanically moved to the substrate areas again and is positioned by the alignment marks of corresponding substrate areas again for cutting the substrate areas of the substrate strips in the second phase. Therefore, an error in any of the substrate areas in the first phase and second phase will not accumulate to the subsequent substrate areas in the substrate strip.

Process for sawing substrate strip

A semiconductor chip package includes an interconnection substrate, a central substrate, a peripheral substrate and a semiconductor chip sandwiched between the interconnection substrate and the central substrate. The interconnection substrate has a recessed cavity for receiving the semiconductor chip. The peripheral substrate is separated from the central substrate thereby decreasing the stresses caused by CTE mismatch of the semiconductor chip package. Furthermore, both the central substrate and the peripheral substrate are mechanically and electrically connected to the interconnection substrate such that the semiconductor chip is electrically connected to the peripheral substrate through the central substrate and the interconnection substrate.

The present invention relates to a quad flat non-leaded package comprising: a lead frame, a semiconductor chip, a plurality of connecting wires and a molding compound. The lead frame has a plurality of leads, a die pad, a plurality of supporting bars and an external ring. The external ring is disposed around the die pad and is in contact with the semiconductor chip so as to increase the supporting to the semiconductor chip. The area of the semiconductor chip is larger than that of the die pad, and the semiconductor chip is attached to the die pad through its active surface. The molding compound encapsulates the lead frame, semiconductor chip and connecting wires, wherein part of the leads of the lead frame is exposed to the outside of the molding compound so as to be electrically connected to an external device.

Quad flat non-leaded package

A leadless semiconductor package disposed on a substrate includes a chip, a plurality of leads, wherein each lead has a metal layer and a first molding compound formed on the metal layer, a second molding compound disposed on the first molding compound, and a chip paddle for carrying the chip. The leads are connected to the chip by wire bonding technique. The metal layer is exposed out of the first molding compound; and the second molding compound encapsulates the chip with the chip paddle exposed out of the second molding compound.

Leadless semiconductor package

A wafer-level package structure, applicable to a flip-chip arrangement on a carrier, which comprises a plurality of contact points, is described. This wafer-level package structure is mainly formed with a chip and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The conductive layer can further be arranged at a region outside the bonding pads on the chip as a heat sink to enhance the heat dissipation ability of the package.

Wafer-level package structure

A semiconductor package mainly comprises a substrate unit and a chip. The chip is electrically connected to the substrate unit. The substrate unit includes an upper surface, a lower surface and a side surface. A plurality of circuit traces are formed on the upper surface and a plurality of contacts are formed on the side surface, wherein the contacts are electrically connected to the circuit traces. Besides, a plurality of solder balls are formed on the contacts in order to transmit the signals from chip to outside through the substrate unit, the contacts and the solder balls. Furthermore, a semiconductor package module will be formed by electrically connecting the semiconductor packages with each other through solder balls and a module substrate, and mounting the semiconductor packages with each other through an adhesive layer. In addition, a method for manufacturing the semiconductor package is disclosed.

Semiconductor package and manufacturing method thereof

A micromachine package includes a first chip, a second chip, a spacer ring, a plurality of bumps, a plurality of leads, and an encapsulant. The first chip has at least one moveable structure. The second chip has at least one electrode for cooperating with the moveable structure of the first chip, and a plurality of pads disposed on one side of the second chip. The spacer ring is disposed between the first chip and the opposite second chip and surrounds the moveable structure. The bumps are disposed on the pads. The lead has a first surface, which is connected to the bumps, and an opposite second surface. The encapsulant encapsulates the first chip, the second chip, the spacer ring, the bumps, and the first surfaces of the leads, and the second surfaces of the leads are exposed out of the encapsulant.

Micromachine package and method for manufacturing the same

An optical component package includes a substrate, an optical component, a plurality of spacers, a plurality of wires, and a transparent molding compound. The optical component is disposed on the substrate, and the surface of the optical component located away from the substrate is used to receive an optical signal. The spacers are disposed between the substrate and optical component. The wires electrically connect the optical component to the substrate. The transparent molding compound encapsulates the optical component. In this case, the diameter of each of the spacers is equal to the thickness of the transparent molding compound minus the thickness of the optical component minus the distance between where the optical signal enters the transparent molding compound and where the optical signal is received by the optical component. Furthermore, this invention also discloses a packaging method for the optical component package.

Optical component package and packaging including an optical component horizontally attached to a substrate

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Kaohsiung, Taiwan

Su Tao