Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Su-Jen Sung

Tze-Liang Lee

Chih-Chiang Chang

Yu-Kai Lin

Chia-Ho Chen

Jen-Hung Wang

Yi-Nien Su

Mei-Ling Chen

Chien-Chung Huang

Po-Cheng Shih

Chao-Chun Wang

Po-Hsiang Huang

Chih-Chien Chi

Hui Yu Lee

Kuo-Chih Lai

Yu-Tsung Lai

Pei-Hsuan Lee

Wen-Sheh Huang

Jen Hung Wang

Jr-Hung Li

Guan-Yao Tu

Wei-Chih Chen

Hong-Wei Chan

Chun-Chieh Huang

Feng-Yu Hsu

Jiann-Jen Chiou

A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.

Semiconductor structure and manufacturing method thereof

A method includes bonding a first wafer to a second wafer, performing a trimming process on the first wafer, and depositing a sidewall protection layer contacting a sidewall of the first wafer. The depositing the sidewall protection layer includes depositing a high-density material in contact with the sidewall of the first wafer. The sidewall protection layer has a density higher than a density of silicon oxide. The method further includes removing a horizontal portion of the sidewall protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.

Highly protective wafer edge sidewall protection layer

A semiconductor device structure is provided. The semiconductor device structure includes a first diffusion barrier layer made of a dielectric material including a metal element, nitrogen, and oxygen and a first protection layer made of a dielectric material including silicon and oxygen and in direct contact with the top surface of the first diffusion barrier layer. The semiconductor device structure also includes a first thickening layer made of a dielectric material including the metal element and oxygen and in direct contact with the top surface of the first protection layer. A maximum metal content in the first thickening layer is greater than that in the first diffusion barrier layer. The semiconductor device structure further includes a conductive feature surrounded by and in direct contact with the first diffusion barrier layer, the first protection layer, and the first thickening layer.

Semiconductor device with multi-layer etch stop structure

Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect. The nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration, the first nitrogen concentration to a second nitrogen concentration, and/or the first number of nitrogen-nitrogen bonds to a second number of nitrogen-nitrogen bonds, each of which minimizes accumulation of copper vacancies at the interface.

Nitrogen plasma treatment for improving interface between etch stop layer and copper interconnect

A method includes forming a transistor over a front side of a substrate; forming a front-side interconnect structure over the transistor, the front-side interconnect structure comprising layers of conductive lines, and conductive vias interconnecting the layers of conductive lines; forming a first bonding layer over the front-side interconnect structure; forming a second bonding layer over a carrier substrate; bonding the front-side interconnect structure to the carrier substrate by pressing the first bonding layer against the second bonding layer; and forming a backside interconnect structure over a backside of the substrate after bonding the front-side interconnect structure to the carrier substrate.

Integrated circuit structure and method for forming the same

An apparatus comprises a first metal feature in a first dielectric layer over a substrate, wherein a sidewall portion of the first dielectric layer is over a top surface of the first metal feature, a second dielectric layer over the first dielectric layer and a second metal feature extending through the second dielectric layer, wherein a bottom of a first portion of the second metal feature is in contact with the top surface of the first metal feature and a bottom of a second portion of the second metal feature is in contact with the sidewall portion of the first dielectric layer.

Interconnect structure and method of forming same

The present disclosure relates to an integrated circuit. The integrated circuit includes a conductive interconnect disposed on a dielectric over a substrate. An interfacial layer is arranged along an upper surface of the conductive interconnect. A liner is arranged along a lower surface of the conductive interconnect. The liner and the interfacial layer surround the conductive interconnect. A middle layer is located over the interfacial layer and has a bottommost surface over the dielectric. A bottommost surface of the interfacial layer and the bottommost surface of the middle layer are both above a top of the conductive interconnect.

Electro-migration barrier for interconnect

A method for forming a semiconductor device structure is provided. The method includes successively forming a first multi-layer etch stop structure and an insulating layer over a first conductive feature. The insulating layer and the first multi-layer etch stop structure are successively etched to form an opening substantially aligned to the first conductive feature. A second conductive feature is formed in the opening. The formation of the first multi-layer etch stop structure and the second multi-layer etch stop structure includes forming a first metal-containing dielectric layer, forming a silicon-containing dielectric layer over the first metal-containing dielectric layer, and forming a second metal-containing dielectric layer over the silicon-containing dielectric layer. The second metal-containing dielectric layer has a material that is different from the material of the first metal-containing dielectric layer.

Method for forming semiconductor device with multi-layer etch stop structure

The present disclosure relates to an integrated circuit having a conductive interconnect disposed on a dielectric over a substrate. A first liner is arranged along an upper surface of the conductive interconnect. A barrier layer is arranged along a lower surface of the conductive interconnect and contacts an upper surface of the dielectric. The barrier layer and the first liner surround the conductive interconnect. A second liner is located over the first liner and has a lower surface contacting the upper surface of the dielectric.

A semiconductor device structure is provided. The structure includes a conductive feature formed in an insulating layer. The structure also includes a first metal-containing dielectric layer formed over the insulating layer and covering the top surface of the conductive feature. The structure further includes a silicon-containing dielectric layer formed over the first metal-containing dielectric layer. In addition, the structure includes a second metal-containing dielectric layer formed over the silicon-containing dielectric layer. The second metal-containing dielectric layer includes a material that is different than the material of the first metal-containing dielectric layer.

Semiconductor device with multi-layer etch stop structure and method for forming the same

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first capping layer on a dielectric structure over a substrate, and patterning the dielectric structure and the first capping layer to define cavities within the dielectric structure. A conductive material is formed within the cavities and a second capping layer is formed on the conductive material. An etch stop layer is formed along sidewalls and over an upper surface of the second capping layer. The etch stop layer has a first thickness over the first capping layer and a second thickness over the second capping layer. The first thickness is greater than the second thickness.

Capping layer for improved deposition selectivity

The present disclosure, in some embodiments, relates to a method of forming an integrated circuit device. The method may be performed by forming a conductive line over a substrate and in contact with a liner. A dielectric barrier layer is formed on the conductive line. The dielectric barrier layer includes an interfacial layer contacting the conductive line, a middle layer contacting the interfacial layer, and an upper layer contacting the middle layer. The interfacial layer and the liner collectively completely surround the conductive line. An inter-level dielectric layer is formed along sidewalls of the upper layer.

Growing community of inventors

Zhubei, Taiwan

Su-Jen Sung