Samsung Electronics Co., Ltd.

Su Hyeong Lee

Hyung Joon Kim

Eun Yeoung Choi

Yong Seok Cho

Jung Geun Jee

A vertical-type memory device includes a plurality of gate electrodes stacked on a substrate; and a vertical channel structure penetrating through the plurality of gate electrodes in a first direction, perpendicular to an upper surface of the substrate. The vertical channel structure includes a channel extending in the first direction, a first filling film that partially fills an internal space of the channel, a first liner on at least a portion of an upper surface of the first filling film and an upper internal side wall of the channel extending beyond the first filling film away from the substrate. The first liner includes n-type impurities. The vertical channel structure includes a second filling film on at least a portion of the first liner, and a pad on the second filling film and in contact with the first liner.

Vertical-type memory device

A semiconductor device includes a plurality of first gate electrodes sequentially stacked on a substrate, a second gate electrode on the plurality of first gate electrodes, a first channel structure extending through the plurality of first gate electrodes and a portion of the second gate electrode, a buried insulation pattern on a sidewall of the first channel structure, of which an upper surface is at a higher level than a top end of the first channel structure, a second channel structure extending through a remainder of the second gate electrode, the second channel structure connected to the first channel structure, and a buried conductive pattern on a sidewall of the second channel structure.

Method of manufacturing three dimensional semiconductor device including first and second channels and buried insulation and conductive patterns

Three dimensional semiconductor device including first and second channels and buried insulation and conductive patterns and method of manufacturing the same

Growing community of inventors

Suwon-si, South Korea

Su Hyeong Lee