Koninklijke Philips Corporation N.v.

Nxp B.v.

Nexperia B.v.

International Rectifier Corporation

Steven Thomas Peake

Philip Rutter

Raymond J Grover

Christopher Martin Rogers

Georgios Petkos

Phil Rutter

Robert J Farr

Peter J Forbes

Ling Ma

Jan Sonsky

David Paul Jones

Dev Alok Girdhar

Brendan P Kelly

Eddie Huang

Yan Lai

Barry Wynne

Miron Drobnis

Andrew Butler

Chris Rogers

Ian Culshaw

David F D Hardy

A semiconductor device and a method of making a semiconductor device. The device includes a semiconductor substrate having a first conductivity type, a layer of doped silicon located on the substrate, a trench extending into the layer of silicon, and a gate electrode and gate dielectric located in the trench. The device also includes a drain region, a body region having a second conductivity type located adjacent the trench and above the drain region, and a source region having the first conductivity type located adjacent the trench and above the body region. The layer of doped silicon in a region located beneath the body region includes donor ions and acceptor ions forming a net doping concentration within said region by compensation. The net doping concentration of the layer of doped silicon as a function of depth has a minimum in a region located immediately beneath the body region.

Semiconductor device and a method of making a semiconductor device

A device is disclosed. The device comprises a substrate having an epitaxial layer of a first conductivity type, a deep trench of a first depth, a pillar region of a second conductivity type of a second depth and a blocking layer of a third conductivity type immediately below a bottom surface of the deep trench. The second depth is larger than the first depth.

TrenchMOS

A process of manufacturing a device is disclosed. The process includes forming an epitaxial layer of a first conductivity type on in a substrate, forming a first vertical section of a second conductivity type in the expitaxial layer, creating a first vertical trench through etching vertically next to the first vertical section, filling the first vertical trench with a first type oxide, forming a second vertical trench in the first vertical trench. The second vertical trench is bounded by the first type oxide in the first vertical trench. The process further includes forming a second type oxide on inner walls of the second vertical trench, filling the second vertical trench with polysilicon. In a second vertical section of the epitaxial layer vertically next to the first vertical trench, a body region is created by implanting ions of the first conductivity type and a source region is created by implanting ions in a top layer of the body region.

PowerMOS

Aspects of the present disclosure are directed to circuitry operable with enhanced capacitance and mitigation of avalanche breakdown. As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves respective transistors of a cascode circuit, one of which controls the other in an off state by applying a voltage to a gate thereof. A plurality of doped regions are separated by trenches, with the conductive trenches being configured and arranged with the doped regions to provide capacitance across the source and the drain of the second transistor, and restricting voltage at one of the source and the drain of the second transistor, therein mitigating avalanche breakdown of the second transistor.

Circuitry with voltage limiting and capactive enhancement

A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.

Trench-gate RESURF semiconductor device and manufacturing method

A device is disclosed. The device includes a semiconductor substrate, a plurality of source lines formed on a surface of the semiconductor substrate. The plurality of source lines are laid in both X and Y directions. The device further includes a plurality of gate lines laid out over source lines in X direction in the plurality of source lines, a source contact line that connects source lines in the plurality of source lines that are terminating in Y direction, a gate contact line that connects the plurality of gate lines and a drain contact.

Semiconductor device having a plurality of source lines being laid in both X and Y directions

A semiconductor uses an isolation trench, and one or more additional trenches to those required for isolation are provided. These additional trenches can be connected between a transistor gate and the drain to provide additional gate-drain capacitance, or else they can be used to form series impedance coupled to the transistor gate. These measures can be used separately or in combination to reduce the switching speed and thereby reduce current spikes.

Semiconductor device having isolation trenches

A trench-gate semiconductor device is disclosed, in which the player () which forms the body region (in a n-channel device) extends adjacent the trench () deeper into the device, to lie adjacent a lower trench electrode (). Since the p-layer extension () forms part of the channel, it must be very low doped, in order not to increase unduly the channel resistance in the on-state. The replacement of some of the out-diffusion resistance in the drift region by the (smaller) channel resistance results in a lower over-all Rdson. In the off-state, the p-layer forms, together with the underlying n-drift layer, a non-abrupt function, so that the depletion region in the off-state extends closer to the top surface () than for a conventional RSO trench-MOS, being split between the p- and n-layers, rather than all being in the n-drift region. The invention does not require a RESURF device structure, so has wide process windows, since the dopant levels and layer thicknesses do not have to be controlled to provide charge balancing.

Trench-gate semiconductor device

An isolation region () is formed between an edge termination region () having deep trenches () and the central region (). The isolation region includes gate fingers () extending from the edge gate trench regions () to the gate trenches () in the central region () to electrically connect the edge gate trench regions to the gate trenches () in the central region. The isolation region also includes isolation fingers () extending from the edge termination region () towards the central region () and gate between the gate fingers () for reducing the breakdown voltage with a RESURF effect.

Edge termination region of a semiconductor device

A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region () of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.

Trench gate MOSFET and method of manufacturing the same

A method of manufacturing an insulated gate field effect transistor includes providing a substrate () having a low-doped region (), forming insulated gate trenches () and implanting dopants of a first conductivity type at the base of the trenches (). A body implant is implanted in the low-doped regions between the trenches; and diffused to form an insulated gate transistor structure in which the body implant diffuses to form a p-n junction between a body region () doped to have the second conductivity type above a drain region () doped to have the first conductivity type, the p-n junction being deeper below the first major surface between the trenches than at the trenches. The difference in doping concentration between the low-doped region () and the implanted region at the base of the trenches causes the difference in depth of the body-drain p-n junction formed in the diffusion step.

Trench field effect transistor and method of making it

An insulated gate field effect transistor has a drain region (), a body region () of opposite conductivity type and a source region () and an insulated gate () extending laterally over the body region (), defining a channel region () extending in the body region () from a source end adjacent to the source region () to a drain end adjacent to a drain end part () of the drain region (). A conductive shield plate () is provided adjacent to the drain end for shielding the gate. Embodiments include a shield plate extension () extending over the drain region from the shield plate () towards the gate ().

Insulated gate field effect transistor

Consistent with an example embodiment, a trench FET has source regions arranged above insulated gates in trenches. A body region of opposite conductivity type is arranged between the trenches and a body region is arranged above the body region. Source contact metallisation contacts the source and body contact region. In this way a small cell pitch can be achieved.

A vertical insulated gate field effect power transistor () has a plurality of parallel transistor cells (TC) with a peripheral gate structure (G, G) at the boundary between each two transistor cells (TC). The gate structure (G, G) comprises first (G) and second (G) gates isolated from each other so as to be independently operable. The first gate (G) is a trench-gate (), and the second gate (G) has at least an insulated planar gate portion (). Simultaneous operation of the first (G) and second (G) gates forms a conduction channel () between source () and drain () regions of the device (). The device () has on-state resistance approaching that of a trench-gate device, better switching performance than a DMOS device, and a better safe operating area than a trench-gate device. The device () may be a high side power transistor is series with a low side power transistor () in a circuit arrangement () (FIG.) for supplying a regulated output voltage. The device () may also be a switch in a circuit arrangement () (FIG.) for supplying current to a load (L). These circuit arrangements () include a terminal (Vcc, V) for applying a supplied fixed potential to an electrode (G) for the first gates (G) and a gate driver circuit () for applying modulating potential to an electrode (G) for the second gates (G).

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Warrington, United Kingdom

Steven Thomas Peake