Fairchild Semiconductor Corporation

National Semiconductor Corporation

Fairchild Semiconductor Corporatiion

Steven Paul Sapp

Dean E Probst

Daniel S Calafut

Hamza Yilmaz

Christopher Boguslaw Kocon

Ashok Challa

Izak Bencuya

Nathan Lawrence Kraft

Peter H Wilson

Duc Q Chau

Bruce Douglas Marchant

Thomas E Grebs

Gary M Dolny

Rodney S Ridley

Brian Sze-Ki Mo

Joseph Andrew Yedinak

Babak S Sani

Chung-Lin Wu

James J Murphy

Alan Elbanhawy

Becky Losee

Bigildis Dosdos

Robert Herrick

Daniel Marvin Kinzer

Oseob Jeon

Qi Wang

Christopher Lawrence Rexer

Gordon K Madson

Suresh Belani

Brian S Mo

John Robert Diroll

Debra S Woolsey

Sunggeun Yoon

Chenming Hu

Rajeev Dinkar Joshi

Consuelo N Tangpuz

Paul Thorup

Mark L Rinehimer

Fred Session

Minhua Li

Ihsiu Ho

Suku Kim

Neill Thornton

Joseph Domenick Montalbo

Sze-Hon Kwan

Dan Kinzer

Hui Chen

Richard Stokes

Mark Larsen

David S Schoenwald

Jason Higgs

Thomas P Welch

Maria Christina B Estacio

Gilmore S Baje

John Mytych

Adam Selsley

Dan Calafut

Seokjin Jo

Rey D Maligro

Bigidis Dosdos

Eugene J Chen

Neil Wylie

Jayson Preece

A first embodiment is a common drain+clip. It has a conventional drain contact on its bottom surface and is flip chip mounted on a half-etched leadframewhich has external source, gate and drain contacts connected to the sources, gate and common drain of the die. Common drain clipconnects the drainto external contacts between opposite gate contacts. A second embodiment is a direct drain embodiment+heatslug. The devicehas a top drain contactthat extends to the common drainacross the bottom of the die which is flip chip mounted to a half-etched leadframe having external source, gate and drain contacts connected to the sources, gates and common drain of the die

Common drain power clip for battery pack protection mosfet

A method can include forming a drift region, forming a well region above the drift region, and forming an active trench extending through the well region and into the drift region. The method can include forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench. The method also includes forming a charge control trench where the charge control trench is aligned parallel to the active trench and laterally separated from the active trench by a mesa region, and where the portion of the well region is in contact with the charge control trench and excludes any source region. The method also includes forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench.

Methods related to power semiconductor devices with thick bottom oxide layers

A field effect transistor (FET) includes a body region of a first conductivity type disposed within a semiconductor region of a second conductivity type and a gate trench extending through the body region and terminating within the semiconductor region. The FET also includes a flared shield dielectric layer disposed in a lower portion of the gate trench, the flared shield dielectric layer including a flared portion that extends under the body region. The FET further includes a conductive shield electrode disposed in the trench and disposed, at least partially, within the flared shield dielectric.

Trench-gate field effect transistor

In one general aspect, a system can include a through-silicon-via (TSV) coupling a drain region associated with a vertical transistor to a back metal disposed on a second side of the substrate opposite the first side. The system can include a first metal layer, and a second metal layer aligned orthogonal to the first metal layer. The system can define a conduction path extending substantially vertically through the TSV to the substrate and laterally through the substrate.

Wafer level MOSFET metallization

A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

Field effect transistor with gated and non-gated trenches

The multi-chip leadless modulehas integrated circuit (IC), dual n-channel mosfet, IC leads, gate leads, and source leads-encapsulated in resin. The ICand the dual n-channel mosfetare mounted face down on the leads. IC leadsare made of planar metal and connect, respectively, to the electrodes TEST, VDD and VM on the ICusing a flip chip technique to assemble the leads on copper pillars or copper studs.

Multi-chip module power clip

In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.

Field effect transistor and schottky diode structures

Field effect transistor with source, heavy body region and shielded gate

In one general aspect, an apparatus can include a polarity insensitive input coupled to a gate of a metal-oxide-semiconductor field effect transistor (MOSFET) device. The MOSFET device can have a gate dielectric rating greater than twenty-five volts. The apparatus can also include a fixed polarity output coupled to a source of the MOSFET device.

Bridge circuit providing a polarity insensitive power connection

Systems and methods of fabricating Wafer Level Chip Scale Packaging (WLCSP) devices with transistors having source, drain and gate contacts on one side of the transistor while still having excellent electrical performance with low drain-to-source resistance R(on) include using a two-metal drain contact technique. The R(on) is further improved by using a through-silicon-via (TSV) technique to form a drain contact or by using a copper layer closely connected to the drain drift.

Vertical MOSFET transistor having source/drain contacts disposed on the same side and method for manufacturing the same

A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Method of manufacture and structure for a trench transistor having a heavy body region

A field effect transistor includes a gate trench extending into a semiconductor region. The gate trench has a recessed gate electrode disposed therein. A source region in the semiconductor region flanks each side of the gate trench. A conductive material fills an upper portion of the gate trench so as to make electrical contact with the source regions along upper sidewalls of the gate trench. The conductive material is insulated from the recessed gate electrode.

Structure and method for forming trench-gate field effect transistor with source plug

A semiconductor die package is disclosed. The semiconductor die package comprises a metal substrate, and a semiconductor die comprising a first surface comprising a first electrical terminal, a second surface including a second electrical terminal, and at least one aperture. The metal substrate is attached to the second surface. A plurality of conductive structures is on the semiconductor die, and includes at least one conductive structure disposed in the at least one aperture. Other conductive structures may be disposed on the first surface of the semiconductor die.

Semiconductor die packages using thin dies and metal substrates

MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral MOSFET devices. A trench-gate provides devices with a single, short channel for high frequency gain. Embodiments of the present invention provide devices with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Refinements to these TG-LDMOS devices include placing a source-shield conductor below the gate and placing two gates in a trench-gate region. These improve device high-frequency performance by decreasing gate-to-drain capacitance. Further refinements include adding a charge balance region to the LDD region and adding source-to-substrate or drain-to-substrate vias.

Trench-gate LDMOS structures

A synchronous buck converter includes a high-side switch and a low-side switch serially coupled to one another. The low-side switch includes a field effect transistor that comprises: a trench extending into a drift region of the field effect transistor; a shield electrode in a lower portion of the trench, wherein the shield electrode is insulated from the drift region by a shield dielectric; a gate electrode in the trench over the shield electrode, wherein the gate electrode is insulated from the shield electrode by an inter-electrode dielectric; source regions adjacent the trench; a source metal contacting the source regions; and a resistive element having one end contacting the shield electrode and another end contacting the source metal in the field effect transistor.

Synchronous buck converter using shielded gate field effect transistors

Growing community of inventors

Felton, CA, United States of America

Steven Paul Sapp