Nec Usa, Inc.

Steven G Rothweiler

Srimat T Chakradhar

Sujit Dey

Vishwani D Agrawal

Miodrag Potkonjak

Vijay Gangaram

A method to significantly accelerate sequential test generation algorithms by accurately computing signal constraints for large sequential circuits and using these constraints effectively during deterministic sequential test generation. The signal constraint computation technique is based on three key ideas: (1) unlike prior techniques (which compute line probabilities assuming only a 0 or 1 value for any signal), line probabilities are computed by allowing signals to assume values other than 0 or 1, (2) line justification techniques are employed to update line probabilities, and (3) symbolic simulation is iteratively used in conjunction with line probability computation and line justification to refine the set of values that a signal can assume. The method results in a significant reduction (more than 50%) in test generation time which is achieved without comprising the fault coverage than can be obtained.

Deriving signal constraints to accelerate sequential test generation

Techniques for the generation of tests for detecting specified faults in circuits that include non-Boolean components and for identifying these undetectable faults that are logically redundant. The main features are: (1) only one Boolean variable is used to represent the value on a signal and all signals assume only Boolean values during the test generation procedure, (2) function of non-Boolean components is separated into Boolean and non-Boolean states, and energy functions are derived only for the Boolean state, and (3) non-Boolean states are implicitly considered in the energy minimization procedure.

Testing and removal of redundancies in VLSI circuits with non-boolean

A technique for optimizing the speed of sequential synchronous digital circuits. First, the bottlenecks that prevent retiming for shortening the delay period are identified and then conditions to eliminate the bottlenecks are derived. This involves identifying the subcircuits associated with the bottlenecks, satisfying a set of timing constraints on the subcircuits, and developing a new circuit that meets the timing constraints. The new circuit free of bottlenecks can generally be retimed by relocation of the forward slack latches to reduce the clock period.

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Kunkletown, PA, United States of America

Steven G Rothweiler