Micron Technology Incorporated

Idaho Research Foundation, Inc.

Steve Kramer

Gurtej S Sandhu

Chien M Wai

Hiroyuki Ohde

Jun Liu

John A Smythe

Mark W Kiehlbauch

Nishant Sinha

A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used to induce a transient stress during programming of the memory cell to reduce the critical switching current of the memory cell.

STT-MRAM cell structure incorporating piezoelectric stress material

Methods and apparatus are provided for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing a composition of magnetic particles dispersed within a base fluid to remove contaminants from a surface of the substrate.

Method for contamination removal using magnetic particles

Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

Spacer process for on pitch contacts and related structures

A mask having features formed by self-organizing material, such as diblock copolymers, is formed on a partially fabricated integrated circuit. A copolymer template, or seed layer, is formed on the surface of the partially fabricated integrated circuit. To form the seed layer, diblock copolymers, composed of two immiscible blocks, are deposited in the space between copolymer alignment guides. The copolymers self-organize, with the guides guiding the self-organization and with each block aggregating with other blocks of the same type, thereby forming the seed layer. Supplemental diblock copolymers are deposited over the seed layer. The copolymers in the seed layer guide self-organization of the supplemental copolymers, thereby vertically extending the pattern formed by the copolymers in the seed layer. Block species are subsequently selectively removed to form a pattern of voids defined by the remaining block species, which form a mask that can be used to pattern an underlying substrate.

Topography based patterning

Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

A mask having features formed by self-organizing material, such as diblock copolymers, is formed on a partially fabricated integrated circuit. Initially, a copolymer template, or seed layer, is formed on the surface of the partially fabricated integrated circuit. To form the seed layer, diblock copolymers, composed of two immiscible blocks, are deposited in the space between copolymer alignment guides. The copolymers are made to self-organize, with the guides guiding the self-organization and with each block aggregating with other blocks of the same type, thereby forming the seed layer. Next, additional, supplemental diblock copolymers are deposited over the seed layer. The copolymers in the seed layer guide self-organization of the supplemental copolymers, thereby vertically extending the pattern formed by the copolymers in the seed layer. Block species are subsequently selectively removed to form a pattern of voids defined by the remaining block species, which form a mask that can be used to pattern an underlying substrate. The supplemental copolymers augment the height of the copolymers in the seed layer, thereby facilitating the use of the copolymers for patterning the underlying substrate.

A method for depositing one or more materials on a substrate, such as for example, a semiconductor substrate that includes providing the substrate; applying a polymer film to at least a portion of a surface of the substrate; and exposing the semiconductor substrate to a supercritical fluid containing at least one reactant for a time sufficient for the supercritical fluid to swell the polymer and for the at least one reactant to penetrate the polymer film. The reactant is reacted to cause the deposition of the material on at least a portion of the substrate. The substrate is removed from the supercritical fluid, and the polymer film is removed. The process permits the precise deposition of materials without the need for removal of excess material using chemical, physical, or a combination of chemical and physical removal techniques.

Method of selectively depositing materials on a substrate using a supercritical fluid

The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid. The supercritical fluid has H, at least one H-activating catalyst, and at least one metal-containing precursor dispersed therein. A metal-containing film is formed across the surface of the semiconductor substrate from metal of the at least one metal-containing precursor. The invention also includes semiconductor constructions having metal-containing layers which include one or more of copper, cobalt, gold and nickel in combination with one or more of palladium, platinum, iridium, rhodium and ruthenium.

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Boise, ID, United States of America

Steve Kramer