Texas Instruments Corporation

Steve Hsia

Douglas Ticknor Grider

Yin Hu

Paul Edward Nicollian

A method to simplify the polycide gate structure fabrication processes by using a hardmask to define a pattern of siliciding a silicon layer and then using the silicide to mask removal of the unreacted silicon and in locations where the hardmask had been present. The metal silicide formed in the exposed silicon regions and functions as a self-aligned mask against the silicon and etching. By using a selective etching process between the silicon and and the silicide , the silicon and can be etched down to the gate oxide to form the polycide (silicide/polysilicon) gate. The polycide gate formed by this method is particularly advantageous in DRAM applications, but can also be used as a MOS gate in a transistor.

Self-aligned stack formation

A composite dielectric layer (102). A first layer (112) of the composite dielectric layer (102) has a small to no nitrogen concentration. A second layer (114) of the composite dielectric layer (102) has a larger nitrogen concentration (e.g., 5-15%). The composite dielectric layer (102) may be used as a thin gate dielectric wherein the second layer (114) is located adjacent a doped gate electrode (110) and has sufficient nitrogen concentration to stop penetration of dopant from the gate electrode (110) to the channel region (108). The first layer (112) is located between the second layer (114) and the channel region (108). The low nitrogen concentration of the first layer (112) is limited so as to not interfere with carrier mobility in the channel region (108).

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Steve Hsia