Integrated Technology Corporation

Steve Clauter

Rodney E Schwartz

Gary B Rogers

Taichi Ukai

David Lohr

Joe Lambright

James Baggiore

Dave Lohr

A device and method for limiting damage to a semiconductor device under test when the semiconductor device fails during a high current, or high power test is provided. The occurrence of a failure of the device under test is detected, and power applied to the semiconductor device is diverted through a parallel path element upon detection of failure of the semiconductor device.

Damage reduction method and apparatus for destructive testing of power semiconductors

A test system, apparatus and method for applying high current test stimuli to a semiconductor device in wafer or chip form includes a plurality of probes for electrically coupling to respective contact points on the semiconductor device, a plurality of current limiters electrically coupled to respective ones of the plurality of probes, and a current sensor electrically coupled to the plurality of probes. The current limiters are operative to limit current flow passing through a respective probe, and the current sensor is operative to provide a signal when detected current in any contact of the plurality of probes exceeds a threshold level.

Probe needle protection method for high current probe testing of power devices

Growing community of inventors

Tempe, AZ, United States of America

Steve Clauter