Intel Corporation

Stephen N Keeney

Gregory E Atwood

Kerry Dean Tedrow

Albert Fazio

Johnny Javanifard

Krishna Kumar Parat

Mark E Bauer

Kenneth E Wojciechowski

Ken Wojciechowski

Kenneth Woiciechowski

A reference voltage generator for a flash memory is described. Specifically, the memory cells used in implementing a reference voltage generator are increased in size to enable the generator to be less sensitive to temperature changes as well as device noise. The flash cells may be coupled to threshold tuning devices, which enable the threshold voltage to be easily trimmed.

Reference voltage generator employing large flash memory cells coupled to threshold tuning devices

A technique of performing post erase repair on a flash memory by identifying a leaky column after the flash memory is erased. The leaky column is repaired first by programming memory cells of the column to increase the threshold voltage Vt of the memory cells to remove the leaky column condition prior to performing post erase repair on the memory cells. Then, each memory cell is verified and repaired to ensure that each memory cell has a Vt above an acceptable post erase repair value. By performing the column leakage repair first, over erased leakage from deselected cells are not present to give false indications when each cell is verified for the post erase repair Vt.

Post erase repair to enhance performance in a flash memory

A method of programming a flash memory cell. The method occurs in a memory device having a decoder that receives a select signal. The decoder is coupled to a first word line and a second word line. The first word line is coupled to a first memory cell and the second word line is coupled to a second memory cell. The select signal is asserted to a first voltage such that the decoder selects the first word line and the first memory cell and deselects the second word line and the second memory cell. The select signal is then asserted to a second voltage such that the decoder couples a programming voltage to the first word line and floats the second word line. The first memory cell is then programmed while the second word line is floating.

Deselected word line that floats during MLC programming of a flash memory

A nonvolatile memory device. For one embodiment, the nonvolatile memory device includes a bit line, a source line, and a nonvolatile memory cell having a drain coupled to the bit line, a source coupled to the source line, a control gate, and a floating gate. The nonvolatile memory device also includes a source voltage generator circuit coupled to the source line and generating a source line voltage when programming the nonvolatile memory cell. The source voltage generator circuit varies the source line voltage based on a location of the nonvolatile memory cell in the memory array. The nonvolatile memory device may also include a drain voltage generator circuit coupled to the bit line and generating a bit line voltage when programming the nonvolatile memory cell. The drain voltage generator circuit varies the bit line voltage based on the location of the nonvolatile memory cell in the memory array.

Flash memory VDS compensation techiques to reduce programming variability

A system and method for programming non-volatile memory enables fast low current programming. Low current programming is achieved by applying a source bias voltage and increasing the drain voltage to be greater than the source bias voltage to maintain fast programming. Furthermore, the control gate voltage may be stepped or ramped from a minimum value to a maximum value to further reduce the peak channel current and to allow the flash cell threshold voltage to be placed to an exact value, for MLC applications. Ramping or stepping of the control gate may be done independently or in conjunction with an applied source bias voltage. Furthermore, the reduced cell current allows more cells to be programmed in parallel which improves program performance and the drain select device can be reduced in size to reduce die area.

Structure and method for low current programming of flash EEPROMs

A voltage regulation circuit that includes a sample and hold circuit for sampling an input voltage and for holding a reference voltage generated in response to the input voltage. The sample and hold circuit includes a capacitor that holds the reference voltage. The voltage regulation circuit also includes a regulator circuit coupled to the capacitor of the sample and hold circuit. The regulator circuit outputs an output voltage using the reference voltage supplied by the capacitor. The voltage regulation circuit may be used to provide a high precision programming voltage for programming memory cells having two or more analog states.

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San Jose, CA, United States of America

Stephen N Keeney