Hewlett-packard Company

Agilent Technologies, Inc.

Stephen Laderman

Theodore I Kamins

James F Gibbons

Douglas A Amorese

Judy L Hoyt

David B Noble

Martin P Scott

Alicia F Scheffer

Clifford A King

Laura Kay Bruhn

The present invention comprises a method of fabricating devices and circuits employing at least one heteroepitaxial layer under strain. The thickness of the heteroepitaxial layer is more than two times the calculated equilibrium critical thickness for an uncapped heteroepitaxial layer upon a crystalline substrate, based on previously known equilibrium theory for the uncapped layer. Subsequent to growth of the heteroepitaxial layer, the structure is processed at temperatures higher than the growth temperature of the heteroepitaxial layer. The strained heteroepitaxial layer (second layer) is epitaxially grown upon the surface of a first, underlaying crystalline layer, creating a heterojunction. Subsequently a third crystalline layer is deposited or grown upon the major exposed surface of the second, strained heteroepitaxial layer. The preferred manner of growth of the third crystalline layer is epitaxial growth. The composition of the third crystalline layer must be such that upon deposition or growth, the third layer substantially continuously binds to the heteroepitaxial structure of the second layer. Subsequent to growth of the at least three layer structure, the structure is processed at temperatures in excess of the growth temperature of the second heteroepitaxial layer. Presence of the third crystalline layer prevents the generation of a substantial amount of misfit dislocations between the first crystalline layer substrate and the second heteroepitaxial layer.

Fabricating a semiconductor device with strained Si.sub.1-x Ge.sub.x

Improved devices with silicon to SiGe alloy heterojunctions are provided for in accordance with the following discoveries. X-ray topography and transmission electron microscopy were used to quantify misfit-dislocation spacings in as-grown Si.sub.1-x Ge.sub.x films formed by Limited Reaction Processing (LRP), which is a chemical vapor deposition technique. These analysis techniques were also used to study dislocation formation during annealing of material grown by both LRP and by molecular beam epitaxy (MBE). The thickness at which misfit dislocations first appear in as-grown material was similar for both growth techniques. The thermal stability of capped and uncapped films was also investigated after rapid thermal annealing in the range of 625.degree. to 1000.degree. C. Significantly fewer misfit dislocations were observed in samples containing an epitaxial silicon cap. Some differences in the number of misfit dislocations generated in CVD and MBE films were observed after annealing uncapped layers at temperatures between 625.degree. and 825.degree. C.

Semiconductor processing with silicon cap over Si.sub.1-x Ge.sub.x Film

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Menlo Park, CA, United States of America

Stephen Laderman