Raytheon Company

Other

Indigo Systems Corporation

Ratheon Company

Stephen H Black

Buu Quoc Diep

Thomas Allan Kocian

Adam M Kennedy

Roland W Gooch

Michael Aidan Gritz

William J Parrish

Robert C Gibbons

Tse E Wong

James T Woolaway, Ii

Richard N Mullins

Gregory D Tracy

Borys Pawel Kolasa

Robert F Burkholder

Roland Gooch

Buu Diep

James T Woolaway

Roger William Graham

Matthew T Kuiken

Richard H Wyles

Jerry A Wilson

Alan G Silver

James A Finch

Paolo Masini

Andrew D Portnoy

Stefan T Baur

Allan M Kennedy

Methods for reducing wafer bow induced by an anti-reflective coating of a cap wafer are provided. The method may utilize a shadow mask having at least one opening therein that is positioned opposite recessed regions in a cap wafer. The method may further include depositing at least one layer of an anti-reflective coating material through the shadow mask onto a planar side of a cap wafer to provide a discontinuous coating on the planar side.

Method of stress relief in anti-reflective coated cap wafers for wafer level packaged infrared focal plane arrays

An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.

Wafer level package solder barrier used as vacuum getter

A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a surface defined by a wafer level package (WLP) region and an external region, and a layer of getter material is disposed on at least a portion of the external region. According to one embodiment, the external region comprises a saw-to-reveal (STR) region of the wafer.

Use of an external getter to reduce package pressure

A sealed package having a device disposed on a wafer structure and a lid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.

Hermetically sealed package having stress reducing layer

According to one aspect, embodiments herein provide a sensing device comprising an accelerometer configured to monitor acceleration of the sensing device and provide acceleration information including a value of the acceleration of the sensing device, and an Integrated Circuit (IC) coupled to the accelerometer, the IC configured to receive the acceleration information from the accelerometer and render the sensing device permanently inoperable in response to the value of the acceleration of the sensing device exceeding a threshold indicative of a military application of the sensing device.

Method and apparatus for inhibiting diversion of devices using an embedded accelerometer

An infrared thermal imaging system includes a focal plane array (FPA) of infrared detectors, read out integrated circuitry (ROIC) operatively coupled to the FPA, and a microcontroller having at least one video display interface operatively coupled to the ROIC. The FPA is configured to generate an output signal in response to infrared radiation impinging upon the infrared detectors. The microcontroller is configured to send data to the ROIC via the at least one video display interface, the data including non-uniformity correction terms for correcting non-uniformities of the FPA.

Infrared thermal imaging system and method

A structure for detecting electromagnetic radiation having a predetermined wavelength. The structure includes a device wafer having a sensing element disposed on a predetermined region of a surface of the device wafer responsive to the electromagnetic radiation. A cover wafer is provided having a region thereof transparent to the electromagnetic radiation for passing the electromagnetic radiation through the transparent region onto a surface of the sensing element. A bond gap spacer structure is provided for supporting the surface of the sensing element from an opposing surface of the transparent region of the cover wafer a distance less than a fraction of the predetermined wavelength when the cover wafer is bonded to the device wafer.

Wafer level packaged infrared (IR) focal plane array (FPA) with evanescent wave coupling

A getter structure and method wherein a layer of seed material is deposited on a predetermined region of a surface of a structure under conditions to form a plurality of nucleation sites on a surface of the structure. The nucleation sites have an average height over the surface area of the predetermined region of less than one molecule thick. Subsequently a getter material is deposited over the surface to form a plurality of getter material members projecting outwardly from the nucleation sites.

Getter structure and method for forming such structure

A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Integrated bondline spacers for wafer level packaged circuit devices

Growing community of inventors

Buellton, CA, United States of America

Stephen H Black