Globalfoundries Inc.

Advanced Micro Devices Corporation

Forschungszentrum Julich Gmbh

Advance Micro Devices, Inc.

Stephan Kronholz

Markus Lenski

Peter Javorka

Maciej Wiatr

Vassilios Papageorgiou

Gunda Beernink

Roman Boschke

Carsten Reichel

Hans-Juergen Thees

Richard Carter

Martin Trentzsch

Matthias Kessler

Annekathrin Zeun

Thorsten E Kammler

Andreas Ott

Ralf Richter

Berthold Reimer

Joachim Patzer

Joanna Wasyluk

Andy C Wei

Andreas Kurz

Frank Seliger

Gisela Schammler

Fernando Koch

Ines Becker

Yew Tuck Chow

Nadja Zakowsky

Paul Raymond Besser

Jan Hoentschel

Rohit Pal

Rolf Stephan

John S Foster

Thomas Feudel

Ricardo Pablo Mikalo

Martin Gerhardt

Christian Krueger

Kerstin Ruttloff

Frank Richter

Markus Forsberg

Joerg Radecker

Boris Bayha

Gregory Nowling

Volker Jaschke

Rainer Giedigkeit

Sven Metzger

Ina Ostermay

Lindarti Purwaningsih

Yew-Tuck Chow

Kai Tern Sih

Berthold Reimes

Andreas Naumann

Falk Graetshe

Silvia Karthäuser

A method for forming field effect transistors (FETs) in a multiple wafers per batch epi-reactor includes, providing substrates having therein at least one semiconductor (SC) region with a substantially flat outer surface, modifying such substantially flat outer surface to form a convex-outward curved surface, forming an epitaxial semiconductor layer on the curved surface, and incorporating the epitaxial layer in a field effect transistor formed on the substrate. Where the SC region is of silicon, the epitaxial layer can include silicon-germanium. In a preferred embodiment, the epi-layer forms part of the FET channel. Because of the convex-outward curved surface, the epi-layer grown thereon has much more uniform thickness even when formed in a high volume reactor holding as many as 100 or more substrates per batch. FETs with much more uniform properties are obtained, thereby greatly increasing the manufacturing yield and reducing the cost.

Epitaxial channel formation methods and structures

A semiconductor device includes drain and source regions positioned in an active region of a transistor and a channel region positioned laterally between the drain and source regions that includes a semiconductor base material and a threshold voltage adjusting semiconductor material positioned on the semiconductor base material. A gate electrode structure is positioned on the threshold voltage adjusting semiconductor material, and a strain-inducing semiconductor alloy including a first semiconductor material and a second semiconductor material positioned above the first semiconductor material is embedded in the semiconductor base material of the active region. A crystalline buffer layer of a third semiconductor material surrounds the embedded strain-inducing semiconductor alloy, wherein an upper portion of the crystalline buffer layer laterally confines the channel region including the sidewalls of the threshold voltage adjusting semiconductor material and is positioned between the second semiconductor material and the threshold voltage adjusting semiconductor material.

Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer

Different strain-inducing semiconductor alloys may be incorporated into the drain and source areas of different transistors in sophisticated semiconductor devices by at least patterning the corresponding cavities in a common manufacturing sequence. Thus, the etch process may be performed on the basis of a high degree of uniformity and the subsequent epitaxial growth processes may, in some illustrative embodiments, be accomplished on the basis of only one additional lithography step.

Integration of semiconductor alloys in PMOS and NMOS transistors by using a common cavity etch process

An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.

Strain engineering in semiconductor devices by using a piezoelectric material

In sophisticated semiconductor devices, transistors may be formed on the basis of a high-k metal gate electrode structure provided in an early manufacturing phase, wherein an efficient strain-inducing mechanism may be implemented by using an embedded strain-inducing semiconductor alloy. In order to reduce the number of lattice defects and provide enhanced etch resistivity in a critical zone, i.e., in a zone in which a threshold voltage adjusting semiconductor alloy and the strain-inducing semiconductor material are positioned in close proximity, an efficient buffer material or seed material, such as a silicon material, is incorporated, which may be accomplished during the selective epitaxial growth process.

Disclosed herein are various methods of forming a silicon/germanium protection layer above source/drain regions of a transistor. One method disclosed herein includes forming a plurality of recesses in a substrate proximate the gate structure, forming a semiconductor material in the recesses, forming at least one layer of silicon above the semiconductor material, and forming a cap layer comprised of silicon germanium on the layer of silicon. One device disclosed herein includes a gate structure positioned above a substrate, a plurality of recesses formed in the substrate proximate the gate structure, at least one layer of semiconductor material positioned at least partially in the recesses, a layer of silicon positioned above the at least one layer of semiconductor material, and a cap layer comprised of silicon/germanium positioned on the layer of silicon.

Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer

A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.

Horizontal epitaxy furnace for channel SiGe formation

A semiconductor device includes a first transistor positioned in and above a first semiconductor region, the first semiconductor region having a first upper surface and including a first semiconductor material. The semiconductor device further includes first raised drain and source portions positioned on the first upper surface of the first semiconductor region, the first drain and source portions including a second semiconductor material having a different material composition from the first semiconductor material. Additionally, the semiconductor device includes a second transistor positioned in and above a second semiconductor region, the second semiconductor region including the first semiconductor material. Finally, the semiconductor device also includes strain-inducing regions embedded in the second semiconductor region, the embedded strain-inducing regions including the second semiconductor material.

Transistor with embedded Si/Ge material having reduced offset and superior uniformity

In sophisticated semiconductor devices, high-k metal gate electrode structures may be formed in an early manufacturing stage with superior integrity of sensitive gate materials by providing an additional liner material after the selective deposition of a strain-inducing semiconductor material in selected active regions. Moreover, the dielectric cap materials of the gate electrode structures may be removed on the basis of a process flow that significantly reduces the degree of material erosion in isolation regions and active regions by avoiding the patterning and removal of any sacrificial oxide spacers.

High-K metal gate electrode structures formed by cap layer removal without sacrificial spacer

Disclosed herein are various methods of forming a layer of silicon on a layer of silicon/germanium. In one example, a method disclosed herein includes forming a silicon/germanium material on a semiconducting substrate, after forming the silicon/germanium material, performing a heating process to raise a temperature of the substrate to a desired silicon formation temperature while flowing a silicon-containing precursor and a chlorine-containing precursor into the deposition chamber during the heating process, and, after the temperature of the substrate reaches the desired silicon formation temperature, forming a layer of silicon on the silicon/germanium material.

Methods of forming a layer of silicon on a layer of silicon/germanium

A semiconductor device includes a gate electrode structure of a transistor, the gate electrode structure being positioned above a semiconductor region and having a gate insulation layer that includes a high-k dielectric material, a metal-containing cap material positioned above the gate insulation layer, and a gate electrode material positioned above the metal-containing cap material. A bottom portion of the gate electrode structure has a first length and an upper portion of the gate electrode structure has a second length that is different than the first length, wherein the first length is approximately 50 nm or less. A strain-inducing semiconductor alloy is embedded in the semiconductor region laterally adjacent to the bottom portion of the gate electrode structure, and drain and source regions are at least partially positioned in the strain-inducing semiconductor alloy.

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode

In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.

Reduction of defect rates in PFET transistors comprising a Si/Ge semiconductor material formed by epitaxial growth

In a stacked chip configuration, the 'inter chip' connection is established on the basis of functional molecules, thereby providing a fast and space-efficient communication between the different semiconductor chips.

Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules

When forming sophisticated semiconductor devices including complementary transistors having a reduced gate length, the individual transistor characteristics may be adjusted on the basis of individually provided semiconductor alloys, such as a silicon/germanium alloy for P-channel transistors and a silicon/phosphorous semiconductor alloy for N-channel transistors. To this end, a superior hard mask patterning regime may be applied in order to provide compatibility with sophisticated replacement gate approaches, while avoiding undue process non-uniformities, in particular with respect to the removal of a dielectric cap layer.

Complementary transistors comprising high-k metal gate electrode structures and epitaxially formed semiconductor materials in the drain and source areas

Growing community of inventors

Dresden, Germany

Stephan Kronholz