Imec Vzw

Interuniversitair Micorelektronica Centrum (imec, Vzw)

Stephan Beckx

Serge Vanhaelemeersch

Stefaan Decoutere

Ludo Deferm

Goncal Badenes

A scaleable device concept and particularly a method for fabrication thereof is disclosed, which allows for a minimal well-controlled gate overlap by using low resistivity source/drain extension regions with shallow junctions. By using such shallow junctions, which are obtained using L-shaped spacers, the gate overlap is no longer dependent on the junction depth of the source/drain contact regions. Particularly the L-shaped spacers are used to locally reduce the penetration depth of the source/drain implantation in the substrate. This concept is particularly interesting for FET's having a channel length below 0.25 &mgr;m because this approach broadens the process window of the silicidation process of the source/drain contact regions. Moreover, the extension regions have to be subjected only to a limited thermal budget.

Method for forming a FET having L-shaped insulating spacers

A method is disclosed for forming a spacer, wherein said formation is preferably performed in a single dry etch sequence in a single dry etch tool. In this single dry etch sequence subsequently polysilicon spacers are defined, used as an etch mask and removed. Said etch sequence comprises at least one dry etching step. In case said etch sequence comprises more than one dry etching step, then these etching steps are performed subsequently in the same etch tool without breaking vacuum in said etch tool. In an embodiment of the invention the capability of using a single dry etch sequence for the formation of nitride spacers, using polysilicon spacer masking and the in-situ removal of the remaining polysilicon spacers, is demonstrated.

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Leuven, Belgium

Stephan Beckx