International Business Machines Corporation

Applied Materials, Inc.

Stephan Alan Cohen

Alfred Grill

Chih-Chao Yang

Stephen McConnell Gates

Sampath Purushothaman

Jane M Shaw

Jeffrey Curtis Hedrick

Son Van Nguyen

Vishnubhai Vitthalbhai Patel

Alessandro Cesare Callegari

Thomas J Haigh, Jr

Devendra K Sadana

Jeffrey P Gambino

Stephen W Bedell

Daniel C Edelstein

Li-Qun Xia

Katherine Lynn Saenger

Kenneth Parker Rodbell

Christopher Vincent Jahnes

Joel Pereira De Souza

Herbert Lei Ho

Elbert Emin Huang

Dirk Pfeiffer

John Anthony Fitzsimmons

Gary Bela Bronner

Vincent James McGahay

Mihaela A Balseanu

Fenton Read McFeely

David M Dobuzinsky

Claudius Feger

Karen A Nummy

Darryl D Restaino

Robert Rosenberg

Eric Gerhard Liniger

John Patrick Hummel

John Jacob Yurkas

Teresita Ordonez Graham

Leena Paivikki Buchwalter

Horatio Seymour Wildman

Jurij R Paraszczak

Ronald R Uttecht

Karen P Madden

Daniel J Poindexter

Cevdet Ismail Noyan

Kevin K Chan

Timothy Joseph Dalton

Hosadurga K Shobha

Fuad Elias Doany

Thomas M Shaw

Xiao Hu Liu

Deborah A Neumayer

Paul Charles Jamison

Kang-Wook Lee

Lynne Marie Gignac

Chester T Dziobkowski

Thomas H Ivers

Eva Erika Simonyi

Edward Paul Barth

Drum stick

Semiconductor devices with low-resistivity metallic interconnect structures are provided. For example, a sacrificial dielectric layer is formed on a substrate, and patterned to form an opening in the sacrificial dielectric layer. The opening is filled with a metallic material to form a metallic interconnect structure, and the sacrificial dielectric layer is removed to expose the metallic interconnect structure. A heat treatment process is applied to the exposed metallic interconnect structure to modulate a microstructure of the metallic material of the metallic interconnect structure from a first microstructure to a second microstructure. A conformal liner layer is selectively deposited on exposed surfaces of the metallic interconnect structure, subsequent to the heat treatment process. A dielectric layer is formed to encapsulate the metallic interconnect structure in dielectric material, wherein the conformal liner layer serves as a diffusion barrier layer between the metallic interconnect structure and the dielectric layer.

Low-resistivity metallic interconnect structures

A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an nsilicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.

[object Object]

A substrate incorporating semiconductor regions electrically isolated by shallow trenches filled with hexagonal, textured or columnar boron nitride. A process for filling shallow trenches in a semiconductor substrate with columnar textured boron nitride using pulsed plasma enhanced chemical vapor deposition (Pulsed PECVD) and plasma assisted atomic layer deposition (PAALD).

Shallow trench isolation for semiconductor devices

An interconnect structure includes a first dielectric material having an undercut region located at an upper surface thereof. A first conductive structure is located above a first area of the undercut region. The first conductive structure comprises a first conductive metal portion having a diffusion barrier portion located on one sidewall surface of the first conductive metal portion and having a metal liner located on another sidewall surface and a bottom surface of the first conductive metal portion. A second conductive structure is located above a second area of the undercut region. The second conductive structure comprises a second conductive material portion having a diffusion barrier portion located on one sidewall surface of the second conductive material portion and having a metal liner located on another sidewall surface and a bottom surface of the second conductive metal portion. A gap is located between the first and second conductive structures.

Nanoscale interconnect structure

Drumstick grip pattern

Drumstick bag

A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues simultaneously form on an exposed upper surface of the interconnect dielectric material. A thermal nitridization process or plasma nitridation process is then performed which partially or completely converts the metallic residues into nitrided metallic residues. During the nitridization process, a surface region of the interconnect dielectric material and a surface region of the metal cap also become nitrided.

Interconnect structures containing nitrided metallic residues

The present disclosure provides a multilayered cap (i.e., migration barrier) that conforms to the substrate (i.e., interconnect structure) below. The multilayered cap, which can be located atop at least one interconnect level of an interconnect structure, includes, from bottom to top, a first layer comprising silicon nitride and a second layer comprising at least one of boron nitride and carbon boron nitride.

Multilayered low k cap with conformal gap fill and UV stable compressive stress properties

A dielectric capping layer having a dielectric constant of less than 4.2 is provided that exhibits a higher mechanical and electrical stability to UV and/or E-Beam radiation as compared to conventional dielectric capping layers. Also, the dielectric capping layer maintains a consistent compressive stress upon post-deposition treatments. The dielectric capping layer includes a tri-layered dielectric material in which at least one of the layers has good oxidation resistance, is resistance to conductive metal diffusion, and exhibits high mechanical stability under at least UV curing. The low k dielectric capping layer also includes nitrogen content layers that contain electron donors and double bond electrons. The low k dielectric capping layer also exhibits a high compressive stress and high modulus and is stable under post-deposition curing treatments, which leads to less film and device cracking and improved device reliability.

Engineered interconnect dielectric caps having compressive stress and interconnect structures containing same

The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween, where the ceramic diffusion barrier has a composition SiNCOH, where 0.1&#x2266;v&#x2266;0.9, 0&#x2266;w&#x2266;0.5, 0.01&#x2266;x&#x2266;0.9, 0&#x2266;y&#x2266;0.7, 0.01&#x2266;z&#x2266;0.8 for v+w+x+y+z=1. The ceramic diffusion barrier acts as a diffusion barrier to metals, i.e., copper. The present invention also comprises a method for forming the inventive ceramic diffusion barrier including the steps depositing a polymeric preceramic having a composition SiNCOH, where 0.1&#x3c;v&#x3c;0.8, 0&#x3c;w&#x3c;0.8, 0.05&#x3c;x&#x3c;0.8, 0&#x3c;y&#x3c;0.3, 0.05&#x3c;z&#x3c;0.8 for v+w+x+y+z=1 and then converting the polymeric preceramic layer into a ceramic diffusion barrier by thermal methods.

Method of forming a ceramic diffusion barrier layer

Growing community of inventors

Wappingers Falls, NY, United States of America

Stephan Alan Cohen