International Business Machines Corporation

Infineon Technologies Ag

Steffen K Kaldor

Timothy Joseph Dalton

Andrew Herbert Simon

Kaushik Arun Kumar

Douglas C La Tulipe, Jr

Mark Hoinkis

Chih-Chao Yang

Lawrence Alfred Clevenger

Erdem Kaltalioglu

Jochen Schacht

Stephen Mark Rossnagel

Yun-Yu Wang

Andrew P Cowley

Clement Hsingjen Wann

Cyril Cabral, Jr

Katherine Lynn Saenger

Sandra Guy Malhotra

Terry Allen Spooner

Chandrasekhar Narayan

David Lee Rath

Shyng-Tsong Chen

Mahadevaiyer Krishnan

Michael F Lofaro

Chao-Kun Hu

Wei-Tsu Tseng

Judith Marie Rubino

Fen Fen Jamin

Kenneth M Davis

Andy Cowley

Hyungjun Kim

Sean P E Smith

Haining S Yang

Soon-Cheon Seo

Conal Eugene Murray

Ismail C Noyan

Larry Clevenger

Mohammed Fazil Fayaz

Anne L Petrosky

An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

Back end interconnect with a shaped interface

In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaN, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.

Method of forming an interconnect structure diffusion barrier with high nitrogen content

A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

Bilayered metal hardmasks for use in dual damascene etch schemes

Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer

A method, apparatus, and computer program product for flattening a warped substrate. The substrate is placed on a planar surface of a clamping apparatus in direct mechanical contact with the planar surface. The substrate comprises surface regions S, S, . . . , Shaving an average warpage of W, W, . . . , W, respectively, wherein W&#x2266;W&#x2266; . . . &#x2266;Wand W&#x2266;W. Zones Z, Z, . . . , Zof the planar surface respectively comprise vacuum port groups G, G, . . . , G. Each group comprises at least one vacuum port. N is at least 2. A vacuum pressure P, P, . . . , Pis generated at each vacuum port within group G, G, . . . , G, at a time of T, T, . . . , Tto clamp surface region S, S, . . . , Sto zone Z, Z, . . . , Z, respectively. The vacuum pressure P, P, . . . , Pis maintained at the vacuum ports of group G, G, . . . , G, respectively, until time T. T&#x3c;T&#x3c; . . . &#x3c;T&#x3c;T.

Apparatus and method for flattening a warped substrate

Interconnect structure diffusion barrier with high nitrogen content

An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

Copper recess process with application to selective capping and electroless plating

Bilayered metal hardmasks for use in Dual Damascene etch schemes

A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 &#x3bc;Ohm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing Nand a flow rate such that (Nflow)/(N+carrier flow)&#x3e;0.5.

Crystallographic modification of hard mask properties

Growing community of inventors

Fishkill, NY, United States of America

Steffen K Kaldor