Infineon Technologies Ag

Stefan Wuensche

Mike A Killian

Harald Streif

A memory device () includes an array () of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder () is coupled to rows of memory cells while a column decoder () is coupled to columns of the memory cells. The column decoder () includes an enable input. A variable delay () has an output coupled to the enable input of the column decoder (). The variable delay () receives an indication (R/W') of whether a current cycle is a read cycle or a write cycle. In the preferred embodiment, a signal provided at the output of the variable delay () is delayed if the current cycle is a read cycle compared to if the current cycle is a write cycle.

Memory device with column select being variably delayed

A memory device () includes an array () of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder is coupled to rows of memory cells while a column decoder () is coupled to columns of the memory cells. The column decoder () includes an enable input. A variable delay () has an output coupled to the enable input of the column decoder (). The variable delay () receives an indication (R/W') of whether a current cycle is a read cycle or a write cycle. In the preferred embodiment, a signal provided at the output of the variable delay () is delayed if the current cycle is a read cycle compared to if the current cycle is a write cycle.

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Sunnyvale, CA, United States of America

Stefan Wuensche