University of California

Transphorm Inc.

Japan Science and Technology Agency

University of Michigan

Cree Gmbh

Agency of Industrial Science and Technology

Stacia Keller

Umesh Kumar Mishra

Steven P DenBaars

Nicholas A Fichtenbaum

Shuji Nakamura

James Stephen Speck

Brian L Swenson

Arpan Chakraborty

Benjamin A Haskell

Srabanti Chowdhury

Rakesh K Lal

Michael D Craven

Tal Margalith

Elaheh Ahmadi

Chirag Gupta

Brian Romanczyk

Matthew Guidry

Jeonghee Kim

Silvia H Chan

Jing Lu

Xun Zheng

Yifeng Wu

Aurelien J F David

Claude C A Weisbuch

Wladyslaw Walukiewicz

Carl Joseph Neufeld

Ramya Yeluri

Xiang Liu

Matthew A Laurent

Bernd Peter Keller

Peter Kozodoy

Christian Wurm

Kamruzzaman Khan

Yusuke Tsukada

Haoran Li

Steven Wienecke

Prashant Chavarkar

Ioulia P Smorchkova

Yuuki Enatsu

Anchal Agarwal

Umesh K Mishra

The disclosure describes the use of strain to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition

III-N based material structures, methods, devices and circuit modules based on strain management

A substrate comprising a III-N base layer comprising a first portion and a second portion, the first portion of the III-N base layer having a first natural lattice constant and a first dislocation density; and a first III-N layer having a second natural lattice constant and a second dislocation density on the III-N base layer, the first III-N layer having a thickness greater than 10 nm. An indium fractional composition of the first III-N layer is greater than 0.1; the second natural lattice constant is at least 1% greater than the first natural lattice constant; a strain-induced lattice constant of the first III-N layer is greater than 1.0055 times the first natural lattice constant; and the second dislocation density is less than 1.5 times the first dislocation density.

Method to control the relaxation of thick films on lattice-mismatched substrates

An electronic device including a substrate a group III-V layer on or above the substrate, wherein the III-V layer has an in-plane lattice constant that is greater than that of gallium nitride or wherein the III-V layer is at least partially relaxed; and an active region including a coherently strained group III-V channel layer on or above the III-V layer; wherein electron mobility in the channel layer is increased by the strain. Structures with an in-plane lattice constant that is smaller than that of gallium nitride are used for increasing the hole mobility by strain.

High mobility group-III nitride transistors with strained channels

Described herein are III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation.

III-N transistor structures with stepped cap layers

An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.

Method to achieve active p-type layer/layers in III-nitrtde epitaxial or device structures having buried p-type layers

A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As A novel design for a nitrogen polar high-electron-mobility transistor (HEMT) structure comprising a GaN/InGaN composite channel. As illustrated herein, a thin InGaN layer introduced in the channel increases the carrier density, reduces the electric field in the channel, and increases the carrier mobility. The dependence of p on InGaN thickness (InGaN) and indium composition (In) was investigated for different channel thicknesses. With optimizedInGaN andIn, significant improvements in electron mobility were observed. For a 6 nm channel HEMT, the electron mobility increased from 606 to 1141 cm/(V&#xb7;s) when the 6 nm thick pure GaN channel was replaced by the 4 nm GaN/2 nm InGaN composite channel.

Structure for increasing mobility in a high electron mobility transistor

Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

Trenched vertical power field-effect transistors with improved on-resistance and breakdown voltage

A transistor includes a III-N layer structure including a III-N channel layer between a III-N barrier layer and a III-N depleting layer, where the III-N channel layer includes a 2DEG channel formed adjacent an interface between the III-N channel layer and the III-N barrier layer; a source and a drain, each of which being directly connected to the III-N channel layer; a gate between the source and the drain, the gate being over the III-N layer structure, where the III-N depleting layer includes a first portion that is disposed in a device access region between the gate and the drain; and where the source electrically contacts the first portion of the III-N depleting layer, and the drain is electrically isolated from the first portion of the III-N depleting layer.

III-Nitride transistor including a III-N depleting layer

A method of fabricating a semiconductor device can include forming a III-N semiconductor layer in a reactor and injecting a hydrocarbon precursor into the reactor, thereby carbon doping the III-N semiconductor layer and causing the III-N semiconductor layer to be insulating or semi-insulating. A semiconductor device can include a substrate and a carbon doped insulating or semi-insulating III-N semiconductor layer on the substrate. The carbon doping density in the III-N semiconductor layer is greater than 5&#xd7;10cmand the dislocation density in the III-N semiconductor layer is less than 2&#xd7;10cm.

Carbon doping semiconductor devices

A transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor further includes a source, a drain, and a gate between the source and the drain, the gate being over the III-N layer structure. The p-type III-N layer includes a first portion that is at least partially in a device access region between the gate and the drain, and the first portion of the p-type III-N layer is electrically connected to the source and electrically isolated from the drain. When the transistor is biased in the off state, the p-type layer can cause channel charge in the device access region to deplete as the drain voltage increases, thereby leading to higher breakdown voltages.

III-nitride transistor including a p-type depleting layer

Embodiments of the present disclosure include a buffer structure suited for III-N device having a foreign substrate. The buffer structure can include a first buffer layer having a first aluminum composition and a second buffer layer formed on the first buffer layer, the second buffer layer having a second aluminum composition. The buffer structure further includes a third buffer layer formed on the second buffer layer at a second interface, the third buffer layer having a third aluminum composition. The first aluminum composition decreases in the first buffer layer towards the interface and the second aluminum composition throughout the second buffer layer is greater than the first aluminum composition at the interface.

Buffer layer structures suited for III-nitride devices with foreign substrates

A method of fabricating a III-nitride semiconductor device, including growing an III-nitride semiconductor and an oxide sequentially to form an oxide/III-nitride interface, without exposure to air in between growth of the oxide and growth of the III-nitride semiconductor.

Metalorganic chemical vapor deposition of oxide dielectrics on N-polar III-nitride semiconductors with high interface quality and tunable fixed interface charge

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Santa Barbara, CA, United States of America

Stacia Keller