Infineon Technologies Ag

Srivatsa Kundalgurki

Hans-Peter Moll

Dietmar Temmler

Joerg Wiedemann

Bottom electrodes of stacked capacitor DRAM cells are formed by depositing a metal layer on the side walls of trenches within a hard mask layer, which serves as a mold for the bottom electrode elements. Prior to depositing the hard mask layer a sacrificial first metal layer is disposed, which results in an electrically conductive surface on the semiconductor wafer. The mask layer is wet-etched to release the bottom electrode as free standing elements on the semiconductor surface. Using the conductive path provided by the first and the second metal layers, the bottom electrodes are polarized in a cleaning liquid bath during a wafer drying process. The generated repulsive electric field overcomes the attractive forces between the neighboring bottom electrode elements induced due to capillary effects of the liquids used for etching and cleaning.

Method for cleaning a semiconductor wafer

Method and apparatus for characterizing a recess located on a surface of a substrate are provided. One embodiment of the invention provides a method for characterizing a recess located on a surface of a substrate. In a first step, a measurement tip is positioned directly above the recess. Subsequently, an electrically conductive path is provided between the measurement tip and the bottom of the recess by ionizing a medium located in the recess. A voltage is applied between the measurement tip and the substrate to measure a current flowing between the measurement tip and the bottom of the recess. The recess is characterized on the basis of the magnitude of the measured current. Another embodiment of the invention provides an apparatus for performing the method for characterizing a recess.

Method and apparatus for characterizing a recess located on a surface of a substrate

The present invention relates to the use of a Cto Calcohol during the cleaning step. With the use of said alcohol, the surface tension of the solution is reduced which allows the application of reduced megasonic power with increased cleaning efficiency.

Enhanced megasonic based clean using an alternative cleaning chemistry

Integrated circuits can include an integrated capacitor with a metal alloy layer. Methods for forming such integrated circuits can include providing a substrate, forming a first electrode including depositing a metal alloy layer having a first surface and an exposed second surface, etching the exposed second surface of the metal alloy layer thereby increasing the surface roughness of the second surface of the metal alloy layer, forming a capacitor dielectric on the first electrode and forming a second electrode on the capacitor dielectric. By providing a metal alloy layer and etching the second surface of the metal alloy layer, an increased capacitance of the integrated capacitor is achieved.

Method for forming a capacitor for an integrated circuit and integrated circuit

Bottom electrodes of stacked capacitor DRAM cells are formed by depositing a metal layer on the side walls of trenches within a hard mask layer, which serves as a mold for the bottom electrode elements. Prior to depositing the hard mask layer a sacrificial first metal layer is disposed, which leads to a electrical conductive surface on the semiconductor wafer. The mask layer is wet-etched to release the bottom electrode as free standing elements on the semiconductor surface. Using the conductive path provided by the first and the second metal layer, the bottom electrodes are polarized in a cleaning liquid bath during a wafer drying process. The generated repulsive electric field overcomes the attractive forces between the neighboring bottom electrode elements induced due to capillary effects of the liquids used for etching and cleaning.

Method for fabricating bottom electrodes of stacked capacitor memory cells and method for cleaning and drying a semiconductor wafer

To fabricate a hole trench storage capacitor having an inner electrode, which is formed in a hole trench, and an outer electrode, which is formed in an electrode section, surrounding the hole trench in a lower section, of the semiconductor substrate, the inner electrode is continued above the substrate surface of the semiconductor substrate. Then, an additional layer, which widens the semiconductor substrate, is grown onto the substrate surface by an epitaxy process. A transition surface for contact-connection of the inner electrode and at least a part of an insulation collar is formed above the original substrate surface, thereby increasing the size of a surface area of the hole trench storage capacitor, which can be used for charge storage, while using the same aspect ratio for an etch used to form the hole trench.

Method for fabricating a hole trench storage capacitor in a semiconductor substrate, and hole trench storage capacitor

Bottom electrodes of stacked capacitor cells are formed by lining a patterned hard mask with a conductive layer. The hard mask is formed by a layered stack. Subsequent to the formation of trenches within the hard mask, the top-most masking layer of the layer stack is laterally recessed. The bottom electrode layer is then deposited to line the trenches. Following this, the bottom electrode layer is removed from the top of the hardmask. Subsequently, the hard mask is removed. As a result, released and free-standing elements of the conductive layer are formed as bottom electrodes that include a hydrophobic contact area in the top part of the bottom electrodes.

Method for fabricating bottom electrodes of stacked capacitor memory cells

The present invention relates to a method for removing a resist selective to a carbon hard mask including providing an etching plasma comprising of at least hydrogen at a predetermined temperature level and a predetermined pressure level in a reaction chamber, and etching the resist selectively to the mask with said plasma for a predetermined period of time.

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Dresden, Germany

Srivatsa Kundalgurki