International Business Machines Corporation

Globalfoundries Inc.

Srinivasa S N Reddy

Rao Venkateswara Vallabhaneni

John Ulrich Knickerbocker

Govindarajan Natarajan

Donald Rene Wall

Charles Leon Arvin

Richard Francis Indyk

John Joseph Garant

Scott Ira Langenthal

Benjamin V Fasano

Eric D Perfecto

Krystyna Waleria Semkow

Brian Richard Sundlof

Robert Anthony Rita

Kevin M Prettyman

Hsichang Liu

Sundar M Kamath

David H Gabriels

Roy Rongqing Yu

Gareth Geoffrey Hougham

Jon Alfred Casey

Minhua Lu

Sung Kwon Kang

Thomas Anthony Wassick

Charles Hampton Perry

Subhash Laxman Shinde

Lester W Herron

Shaji Farooq

Sarah Huffsmith Knickerbocker

Kamalesh K Srivastava

James N Humenik

Thomas Edward Lombardi

Peter Jeffrey Brofman

Lawrence D David

Harry David Cox

Donald W Henderson

Robert William Pasco

Mukta S Farooq

Julien Sylvestre

Arthur Gilman Merryman

Renee L Weisman

Charles C Goldsmith

Renuka S Divakaruni

Richard A Shelleman

Anthony Mastreani

Vivek M Sura

Alexandre Blander

Scott Partington

Farid Youssif Aoude

Carla A Bailey

Jerry A Gorrell

Martin E Klepeis

Hal Mitchell Lasky

Kenneth Bird

Clare J McCarthy

Hua Gan

Vall F McClean

Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal.

Electromigration-resistant lead-free solder interconnect structures

In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.

Additives for grain fragmentation in Pb-free Sn-based solder

One embodiment of the present invention is directed to an under bump metallurgy material. The under bump metallurgy material of this embodiment includes an adhesion layer and a conduction layer formed on top of the adhesion layer. The under bump metallurgy material of this embodiment also includes a barrier layer plated on top of the conduction layer and a sacrificial layer plated on top of the barrier layer. The conduction layer of this embodiment includes a trench formed therein, the trench contacting a portion of the barrier layer and blocking a path of intermetallic formation between the conduction layer and the sacrificial layer.

Intermetallic diffusion block device and method of manufacture

A method is provided for the making of interconnect solder bumps on a wafer or other electronic device. The method is particularly useful for the well-known C4NP interconnect technology and determines if any off-set resulted between the solder mold array and the wafer capture array during the transfer process. The amount of off-set enables the operator to adjust the transfer tool before solder transfer to compensate for the off-set caused by the transfer process and provides a more cost-effective and efficient solder transfer process. A solder reactive material surrounding the capture pads is used to determine where the solder reacts with the solder reactive material showing the off-set resulting from the transfer process. Copper is a preferred solder reactive material.

Alignment verification for C4NP solder transfer

An apparatus and a method are disclosed for providing point of care testing for osmolarity of a bodily fluid. An apparatus is disclosed as having a fluid pathway passing through it for receiving and testing a sample fluid. The invention permits osmolarity testing of a sample fluid wherein the sample fluid has a volume of less than approximately 30 nL, and implements a method and device to measure fluid osmolarity in a clinical setting quickly and accurately, while also reducing evaporation of the fluid.

Method and apparatus for point of care osmolarity testing

The present invention relates generally to a new dielectric forming metal/ceramic laminate magnet and process thereof. More particularly, the invention encompasses a new process for fabrication of a large area laminate magnet with a significant number of holes, integrated dielectric forming metal plate(s) and electrodes for electron and electron beam control. The present invention also relates to a magnetic matrix display and electron beam source and methods of manufacture thereof.

Discrete magnets in dielectric forming metal/ceramic laminate and process thereof

The present invention discloses a CVD (Chemical Vapor Deposition) process where nickel or alloys thereof, such as, Ni/Cu, Ni/Co, are deposited on metal surfaces which are capable of receiving nickel or alloys thereof, using an Iodide source, preferably an Iodide salt, such as, Ammonium Iodide or Copper Iodide, with at least one inert stand-off in contact with the receiving metal surface. This invention basically allows the CVD of nickel (Ni) on molybdenum (Mo) or tungsten (W) where the nickel source is physically isolated from the refractory metal surface to be plated using at least one inert material that is in floating contact with the refractory metal surface that needs to be coated with at least one layer of nickel or alloy thereof.

CVD of metals capable of receiving nickel or alloys thereof using inert contact

A paste for one of a via and an external feature, such as a pad, tab, or line, of a ceramic substrate, includes at least one of titania and zirconia, and a filler material mixed with the at least one of titania and zirconia. Further, the via structure or external feature such as an input/output pad, tab, or line, includes a metallic plating thereover. A method of forming the via structure or the external feature on the ceramic substrate, includes steps of either depositing the paste in the via of the ceramic substrate or depositing the paste on the ceramic substrate, and depositing, by a dry process metallic plating, a metallic plating on the paste. The paste includes at least one of titania and zirconia for reducing residual stress without effecting the platability of the metallic plating.

Method of forming features on a ceramic substrate using platible pastes

The present invention relates generally to a new metal/ceramic laminate magnet and process thereof. More particularly, the invention encompasses a new process for fabrication of a large area laminate magnet with a significant number of holes, integrated metal plate(s) and electrodes for electron and electron beam control. The present invention also relates to a magnetic matrix display and electron beam source and methods of manufacture thereof.

Process of forming metal/ferrite laminated magnet

The present invention relates generally to a new metal/magnetic-ceramic laminate with through-holes and process thereof. More particularly, the invention encompasses a new process for fabrication of a large area ceramic laminate magnet with a significant number of holes, integrated metal plate(s) and co-sintered electrodes for electron and electron beam control. The present invention also relates to a magnetic matrix display (MMD), and electron beam source, and methods of manufacture thereof.

Low temperature sintering of ferrite materials

A cost-effective surface metallization structure of a TCA carrier is produced by using a high-grit conducting paste to fill TSM vias in the TSM of the TCA carrier. This concept can be applied to alumina substrates with refractory metal conductors or to LCGC substrates with more noble metal conductors.

Surface metallization structure for multiple chip test and burn-in

A copper-based paste is disclosed for filling vias in, and forming conductive surface patterns on, ceramic substrate packages for semiconductor chip devices. The paste contains copper aluminate powder in proper particle size and weight proportion to achieve grain size and shrinkage control of the via and thick film copper produced by sintering. The shrinkage of the copper material during sintering is closely matched to that of the ceramic substrate.

Copper-based paste containing copper aluminate for microstructural and shrinkage control of copper-filled vias

The capacitor on a ceramic substrate one by unique film metallization including in one embodiment an in situ oxidation of titanium to create a metal oxide capacitor. The combination of metals when used with the appropriate optimized oxidation conditions and parameters ensures a high yielding capacitor with high capacitance in absence of noble metals and with ease of manufacture providing a low cost, high yield capacitor on ceramic.

Thin film capacitor on ceramic

A semiconductor chip interposer increases fatigue life of interconnections between a first component having a relatively high thermal coefficient of expansion (TCE) and a second component having a relatively low TCE. The semiconductor chip interposer includes a thin metal plate having a plurality of through holes, the thin metal plate having a TCE intermediate the relatively high TCE and the relatively low TCE. An insulation coating on the thin metal plate is also included on walls of the through holes. An electrical conductive material fills each of the insulated through holes for electrical interconnection between the first component and the second component.

Enhanced interconnection to ceramic substrates

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Lagrangeville, NY, United States of America

Srinivasa S N Reddy