Globalfoundries Inc.

Freescale Semiconductor,inc.

Motorola Corporation

Globalfoundries U.S. Inc.

International Business Machines Corporation

Samsung Electronics Co., Ltd.

Srikanth Balaji Samavedam

Laegu Kang

Yi Qi

Manfred Eller

Michael Ganz

Puneet Khanna

Sri Charan Vemula

William James Taylor, Jr

James Kenyon Schaeffer, Iii

Gauri V Karve

Philip J Tobin

Jagar Singh

Michael John Hargrove

David Gilmer

Vara Govindeswara Reddy Vakada

Cristiano Capasso

Yanxiang Liu

Richard J Carter

Christian Gruensfelder

Manoj Joshi

Vara G Reddy Vakada

Mark Douglas Hall

Shesh Mani Pandey

Suresh Venkatesan

Olubunmi O Adetutu

Jin Ping Liu

Rohit Pal

Da Zhang

Bruce E White

Christopher C Hobbs

Johannes M Van Meer

Bongki Lee

Mark Victor Raymond

Ruilong Xie

Takashi Ando

Hui Zang

Julien Frougier

Xiangdong Chen

Kisik Choi

Ramachandran Muralidhar

Mahbub Rashed

Victor Chan

Michael Alan Sadd

Voon-Yew Thean

Subramani Kengeri

David L O'Meara

Jun Yuan

Frank Scott Johnson

Nam Sung Kim

Andreas Knorr

Seunghwan Lee

Navneet Jain

Rama I Hegde

Baofu Zhu

Nigel Graeme Cave

John M Grant

David Doman

Xiaodong Yang

Narasimhulu Kanike

Eric D Luckowski

Sucharita Madhukar

Bo Jiang

Kuldeep Amarnath

Arturo Manuel Martinez, Jr

William J Taylor

Luigi Pantisano

Anvitha Shampur

Hans Van Meer

Muhammad Rahman

Choongryul Ryou

Eric J Verret

One illustrative Schottky diode disclosed herein includes a semiconductor substrate, an anode region and a cathode region. The anode region includes a plurality of first fins with a first vertical height formed in the anode region, wherein an upper surface of the semiconductor substrate is exposed within the anode region. The cathode region includes a plurality of second fins with a second vertical height that is greater than the first vertical height. The device also includes a conductive structure that contacts and engages at least an upper surface of the plurality of first fins in the anode region.

Fin-based Schottky diode for integrated circuit (IC) products and methods of making such a Schottky diode

A semiconductor device is disclosed including a semiconductor layer, a first well doped with dopants of a first conductivity type defined in the semiconductor layer, a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the semiconductor layer adjacent the first well to define a PN junction between the first and second wells, and an isolation structure positioned in the second well. The semiconductor device also includes a first source/drain region positioned in the first well, a second source/drain region positioned in the second well adjacent a first side of the isolation structure, a doped region positioned in the second well adjacent a second side of the isolation structure, and a gate structure positioned above the semiconductor layer, wherein the gate structure vertically overlaps a portion of the doped region.

Semiconductor device with doped region adjacent isolation structure in extension region

An illustrative device includes a transistor including a first set of fins defined above a substrate, a second set of fins defined above the substrate, and a gate structure embedded in the substrate between the first set of fins and the second set of fins, wherein the first set of fins and the second set of fins are doped with a first dopant type and the substrate is doped with a second dopant type different than the first dopant type.

High voltage transistor with fin source/drain regions and trench gate structure

Disclosed are methods of forming a semiconductor structure including a bulk semiconductor substrate and, on the substrate, a fin-type field effect transistor (FINFET) with a uniform channel length and a below-channel buried insulator. In the methods, a semiconductor fin is formed with a sacrificial semiconductor layer between lower and upper semiconductor layers. During processing, the sacrificial semiconductor layer is replaced with dielectric spacer material (i.e., a buried insulator). The buried insulator functions as an etch stop layer when etching source/drain recesses, ensuring that they have vertical sidewalls and, thereby ensuring that the channel region has a uniform length. The buried insulator also provides isolation between channel region and the substrate below and prevents dopant diffusion into the channel region from a punch-through stopper (if present). Optionally, the buried insulator is formed so as to contain an air-gap. Also disclosed are structures resulting from the methods.

Fin-type field effect transistors with uniform channel lengths and below-channel isolation on bulk semiconductor substrates and methods

A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.

Transistor device structures with retrograde wells in CMOS applications

One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, forming a gate structure around the fin and, after forming the gate structure, forming a final source/drain cavity in the fin, wherein the source/drain cavity includes an upper innermost edge and a lower innermost edge, both of which extend laterally under at least a portion of the gate structure, and wherein the lower innermost edge extends laterally further under the gate structure than does the upper innermost edge. The method also includes performing an epitaxial growth process to form an epi semiconductor material in the final source/drain cavity.

Methods of forming source/drain regions on FinFET devices

A method for producing a finFET having a fin with thinned sidewalls on a lower portion above a shallow trench isolation (STI) regions is provided. Embodiments include forming a fin surrounded by STI regions on a substrate; recessing the STI regions, revealing an upper portion of the fin; forming a spacer over side and upper surfaces of the upper portion of the fin; recessing the STI regions, exposing a lower portion of the fin; and thinning sidewalls of the lower portion of the fin.

FinFET device and method of manufacturing

A static random access memory (SRAM) cell includes 1and 2fins disposed on a substrate. A 1pass gate transistor (1PG) is embedded in the 1fin. The 1PG has a source region and a drain region disposed over the 1and 2fins. A 1gate structure (1PG-G) is disposed over the 1fin and between the source and drain regions. The 1PG-G is electrically connected to a 1word line. A 2pass gate transistor (2PG) is embedded in the 2fin. The 2PG has the same source and drain regions. A 2gate structure (2PG-G) is disposed over the 2fin and between the source and drain regions. The 2PG-G is electrically connected to a 2word line. A 1CT pillar is disposed between the 1PG-G and 2PG-G.

SRAM cell having dual pass gate transistors and method of making the same

One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region.

Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures

Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).

Integrated circuits with varying gate structures and fabrication methods

Co-fabrication of a radio-frequency (RF) semiconductor device with a three-dimensional semiconductor device includes providing a starting three-dimensional semiconductor structure, the starting structure including a bulk silicon semiconductor substrate, raised semiconductor structure(s) coupled to the substrate and surrounded by a layer of isolation material. Span(s) of the layer of isolation material between adjacent raised structures are recessed, and a layer of epitaxial semiconductor material is created over the recessed span(s) of isolation material over which another layer of isolation material is created. The RF device(s) are fabricated on the layer of isolation material above the epitaxial material, which creates a local silicon-on-insulator, while the three-dimensional semiconductor device(s) can be fabricated on the raised structure(s).

Dual three-dimensional and RF semiconductor devices using local SOI

In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.

Integration method for fabrication of metal gate based multiple threshold voltage devices and circuits

Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

Epitaxially forming a set of fins in a semiconductor device

A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.

Blanket EPI super steep retrograde well formation without Si recess

In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.

Integrated circuit having multiple threshold voltages

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Fishkill, NY, United States of America

Srikanth Balaji Samavedam