Intel Corporation

Srikant Nekkanty

Donald Tiendung Tran

Zhichao Zhang

Joshua Heppner

Feroz Mohammad

Kemal Aygun

Steven A Klein

Michael Garcia

Joe F Walczyk

Gaurav Chawla

Kuang C Liu

Gregorio R Murtagian

Debendra Mallik

Ravindranath Vithal Mahajan

Pooya Tadayon

Russell S Aoki

Jeffory L Smalley

Vladimir K Tamarkin

Ling Liao

Andrew Alduino

Glen Patrick Gordon

Wesley Brook Morgan

David Hui

Feifei Cheng

Suresh V Pothukuchi

Divya Pratap

Sushrutha Reddy Gujjula

Zhe Chen

Sarah M Canny

Harinadh Potluri

David M Bond

Dhanya Athreya

Adel A Elsherbini

Shawna M Liff

Sasha N Oster

Nitin A Deshpande

Saikumar Jayaraman

Michael C Ryan

Yoshihiro Tomita

Rajasekaran Swaminathan

Hong Xie

Rajendra C Dias

Sriram Srinivasan

Thomas A Boyd

Paul J Diglio

Manish Dubey

Xiaoqian Li

Changhua Liu

Liang Zhang

Todd R Coons

Kevin Ceurter

Patrick Nardi

Karumbu Meyyappan

Eric J Moret

Morten S Jensen

Srinivasa R Aravamudhan

Michael E Ryan

Alexander W Huettis

Zuyang Liang

Vineeth Abraham

Yong Wang

Hemant Mahesh Shah

Yoko Sekihara

A microelectronic socket structure and a method of forming the same. The socket structure comprises: a socket structure housing defining a cavity therein; and an interconnection structure including: a contact element disposed at least in part within the cavity, and configured to be electrically coupled to a corresponding microelectronic package, the contact element corresponding to one of a signal contact element or a ground contact element; and a conductive structure disposed at least in part within the cavity, electrically coupled to the contact element, and having an outer contour that is non-conformal with respect to an outer contour of the contact element.

Heterogenous socket contact for electrical and mechanical performance scaling in a microelectronic package

Embodiments described herein may be related to apparatuses, processes, and techniques related to micro socket arrays with fine pitch contacts to electrically couple dies, in particular photonics dies, within multichip photonics packages. In embodiments, micro socket arrays may be used in conjunction with multichip module packaging that include silicon photonic engines and optical fiber modules on the same package. In embodiments, these packages may also use a system on chip (SOC), as well as fine pitch die to die connections, for example an EMIB, that may be used to connect a PIC with an SOC. Other embodiments may be described and/or claimed.

Micro socket electrical couplings for dies

Techniques and mechanisms for facilitating horizontal communication with a photonic integrated circuit (PIC) chip, and a lens structure which is optically coupled thereto. In an embodiment, a PIC chip comprises integrated circuitry, photonic waveguides, and integrated edge-oriented couplers (IECs) which are coupled to the integrated circuitry via the photonic waveguides. The PIC chip forms respective first divergent lens surfaces of the IECs, which are each at a respective terminus of a corresponding one of the photonic waveguides. A lens structure, which is adjacent to the IECs, comprises a second divergent lens surface having an orientation which is substantially orthogonal to the respective orientations of the first divergent lens surfaces. In another embodiment, an edge of the PIC chip forms one or more recess structures, and the lens structure comprises one or more tenon portions which each extends into a respective recess structure of the one or more recess structures.

Device, method and system for optical communication with a photonic integrated circuit chip and a transverse oriented lens structure

Embodiments disclosed herein include photonics packages and systems. In an embodiment, a photonics package comprises a package substrate, where the package substrate comprises a cutout along an edge of the package substrate. In an embodiment, a photonics die is coupled to the package substrate, and the photonics die is positioned adjacent to the cutout. In an embodiment, the photonics package further comprises a receptacle for receiving a pluggable optical connector. In an embodiment, the receptacle is over the cutout.

Package expanded beam connector for on-package optics

Embodiments described herein may be related to apparatuses, processes, and techniques related to active optical couplers that provide optical coupling at or proximate to an edge of a silicon photonics package, to allow the package to optically couple with other devices or peripherals. In embodiments, the active optical coupler is optically coupled with a photonics IC (PIC) inside the photonics package, and provides an optical coupling mechanism for optical pathways outside the photonics package. The active optical coupler may include electrical circuitry and may be coupled to the package substrate to provide data related to the operation of the active optical coupler. Other embodiments may be described and/or claimed.

Active optical coupler

Techniques and mechanisms for coupling packaged devices with a socket device. In an embodiment, the socket device comprises a socket body structure and conductors extending therethrough. A pitch of the conductors is in a range of between 0.1 millimeters (mm) and 3 mm. First and second metallization structures also extend, respectively, from opposite respective sides of the socket body structure. In the socket body structure, a conductive shield structure, electrically coupled to the first and second metallization structures, substantially extends around one of the conductors. For each of the first and second metallization structures, a vertical span of the metallization structure is in a range of between 0.05 mm and 2.0 mm, a portion of a side of the metallization structure forms a respective corrugation structure, and a horizontal span of the portion is at least 5% of the vertical span of the metallization structure.

Dual-sided socket device with corrugation structures and shield structures

An interconnect that has an electrically conductive layer, where a first and second insulator layers are coupled with the conductive layer. A region of the conductive layer includes an opening of a portion of the first insulator layer the second insulator layer that are adjacent to the region. An electrical connector of a first device is electrically coupled to a portion of the region on a first side of the conductive layer and an electrical conductor of a second device is electrically coupled with a portion of the region on the second side. Also, an interconnect coupled with a substrate that includes a cylinder extending from a side of the substrate with a plate coupled at the end of the cylinder with an opening that includes two or more tabs of the plate extending into the opening to receive a connector.

Electrical connector with insulated conductive layer

Techniques and mechanisms for coupling packaged devices with a dual-sided socket device. In an embodiment, two interfaces of the socket device comprise, respectively, first metallization structures and second metallization structures on opposite sides of a socket body structure. The first metallization structures each form a respective corrugation structure to electrically couple with a corresponding conductive contact of a first packaged device. The corrugation structures facilitate such electrical coupling each via a vertical wipe of the corresponding conductive contact. In another embodiment, a pitch of the first metallization structures is in a range of between 0.1 millimeters (mm) and 2 mm. One such metallization structure has a vertical span in a range of between 0.05 mm and 2.0 mm, where a portion of a side of the metallization structure forms a corrugation structure, and has a horizontal span which is at least 5% of the vertical span.

Dual-sided socket device with corrugation structures

Embodiments include assemblies. An assembly includes a substrate having a first interconnect and a second interconnect. The first interconnect has a first conductive pad and a second conductive pad, and the second interconnect has a third conductive pad and a fourth conductive pad. The assembly includes a socket over the substrate. The socket has a first pin, a second pin, and a base layer with a first pad and a second pad. The first and second pins are vertically over the respective first and second interconnects. The first pad is directly coupled to the first pin and fourth conductive pad, while the second pad is directly coupled to the second pin and second conductive pad. The first pad is positioned partially within a footprint of the third conductive pad, and the second pad is positioned partially within a footprint of the first conductive pad.

Differential crosstalk self-cancelation in stackable structures

Embodiments disclosed herein include electronic packages for optical to electrical switching. In an embodiment, an electronic package comprises a first package substrate and a second package substrate attached to the first package substrate. In an embodiment, a die is attached to the second package substrate. In an embodiment, a plurality of photonics engines are attached to a first surface and a second surface of the first package substrate. In an embodiment, the plurality of photonics engines are communicatively coupled to the die through the first package substrate and the second package substrate.

Dual-sided co-packaged optics for high bandwidth networking applications

The present disclosure relates to a method including providing a die including a cavity therein, wherein the die further may include a die fiducial on a top surface. The method further includes placing a lens structure in the cavity of the die, wherein the lens structure may include a lens fiducial on a front surface. The method also includes moving the lens structure in the cavity to a position until a lens fiducial image may be captured in an image processing system when the lens fiducial and the die fiducial coincide and lie in a plane orthogonal to the top surface of the die. A corresponding system is also disclosed herein.

Method and device for fast, passive alignment in photonics assembly

Systems, apparatus, and/or processes directed to applying pressure to a socket to alter a shape of the socket to improve a connection between the socket and a substrate, printed circuit board, or other component. The socket may receive one or more chips, may be an interconnect, or may be some other structure that is part of a package. The shape of the socket may be flattened so that a side of the socket may form a high-quality physical and electrical coupling with the substrate.

Pressure features to alter the shape of a socket

An interposer and method of providing spatial and arrangement transformation are described. An electronic system has an electronic package, a motherboard and an interposer between the package and the motherboard. The interposer has signal and ground contacts on opposing surfaces that are respectively connected. The contacts opposing the package has a higher signal to ground contact ratio than the contacts opposing the motherboard, as well as different arrangements. Ground shielding vias in the interposer, which are connected to a ground plane, electrically isolate the signals through the interposer. The package may be mounted on a shielded socket such that signal and ground pins are mounted respectively in signal and ground socket mountings, ground shielding vias are between the signal socket mountings, and the ground socket mountings contain plated socket housings.

Pin count socket having reduced pin count and pattern transformation

Growing community of inventors

Chandler, AZ, United States of America

Srikant Nekkanty