Intel Corporation

Sridhar Balakrishnan

Valery M Dubin

Mark T Bohr

Patrick R Morrow

Qing Ma

Paul B Fischer

Jun He

Guanghai Xu

Satish Radhakrishnan

Kevin O'Brien

Jian Li

Xiao-Chun Mu

Tatyana N Andryushchenko

James S Clarke

Boyan Boyanov

Hui Jae Yoo

Christopher J Jezewski

Ramanan Chebiam

Sean W King

Jeffery D Bielefeld

Steven W Johnston

Chin-Chang Cheng

Rohan N Akolkar

Philip Yashar

Sohail U Ahmed

Rickie L Davis

Tatyana T Adryushchenko

Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

Designs and methods for conductive bumps

The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.

Debond interconnect structures

Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.

Barrier layers

Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at least one alloying element in the barrier precursor to form a dielectric barrier between the wire and the ILD. The dielectric barrier is therefore a self-forming, self-aligned barrier. Thermal processing is done under conditions to cause the at least one alloying element to migrate from a zone of higher concentration thereof to a zone of lower concentration thereof to further form the dielectric barrier. Various apparatus are made by the process.

Self-forming, self-aligned barriers for back-end interconnects and methods of making same

A spacer is adjacent to a conductive line. Vias that do not completely land on the conductive line land on the spacer and do not punch through into a volume below the spacer.

Air-gap ILD with unlanded vias

Methods of fabricating interconnect structures utilizing barrier material layers formed with an electroless deposition technique utilizing a coupling agent complexed with a catalytic metal and structures formed thereby. The fabrication fundamentally comprises providing a dielectric material layer having an opening extending into the dielectric material from a first surface thereof, bonding the coupling agent to the dielectric material within the opening, and electrolessly depositing the barrier material layer, wherein the electrolessly deposited barrier material layer material adheres to the catalytic metal of the coupling agent.

Conformal electroless deposition of barrier layer materials

A method for forming a semiconductor device is disclosed wherein atomic layer deposition (ALD) precursor species and/or by-product absorbed by an ILD are outgassed and/or neutralized prior to subsequently patterning the semiconductor device, thereby improving the ability to accurately define subsequently formed interconnect structures in the ILD.

Post polish anneal of atomic layer deposition barrier layers

Methods and apparatuses are disclosed in which a refractory layer is formed during rapid thermal processing wherein ambient hydrogen is used in the thermal processing chamber. Rapid thermal processing may occur at a temperature approximately in the range of 350&deg; C. to approximately 550&deg; C.

Method and an apparatus for forming an under bump metallization structure

One embodiment of the invention involves a refractory layer formed over a substrate during rapid thermal processing in which ambient hydrogen is used in a thermal processing chamber. Rapid thermal processing may occur at a temperature approximately in the range of 350&deg; C. to approximately 550&deg; C.

Growing community of inventors

Portland, OR, United States of America

Sridhar Balakrishnan