Texas Instruments Corporation

Sreenivasan Kalyani Koduri

Benjamin Stassen Cook

Leslie Edward Stark

Nazila Dadvand

Christopher Daniel Manack

Steven Alfred Kummerl

Ralf Jakobskrueger Muenster

Lance Cole Wright

Ashish Khandelwal

Frank Stepniak

Nikhil Gupta

Timothy W Fischer

Matthew David Romig

Subhashish Mukherjee

Edgar Rolando Zuniga-Ortiz

Benjamin Michael Sutton

David Joseph Bon

Scott Robert Summerfelt

Rajeev Dinkar Joshi

Anindya Poddar

Yogesh Kumar Ramadass

Rajen Manicon Murugan

Yiqi Tang

Jeffrey Anthony Morroni

Abram M Castro

Paul L Brohlin

Siva Prakash Gurrum

Sujan Kundapur Manohar

Amit Sureshkumar Nangia

Wai Lee

Charles K Harris

Sylvester Ankamah-Kusi

Ubol Udompanyavit

Gerald William Steele

Steven R Tom

Jason Marc Cole

Matthew J Stovall

Taylor R Efland

Robert Allan Neidorff

Mutsumi Masumoto

Manoj K Jain

Michael G Amaro

Kenji Masumoto

Balamurugan Subramanian

Richard J Saye

Eduardo Bartolome

Joe D Woodall

Yee Hsun U

Joe Douglas Woodall

David Ho

Michael L Meyers

Scott F Eisenhart

Grimmett Dale Jacky

A technique for designing circuits including receiving a data object representing a circuit for a first process technology, the circuit including a first sub-circuit, the first sub-circuit including a first electrical component and a second electrical component arranged in a first topology; identifying the first sub-circuit in the data object by comparing the first topology to a stored topology, the stored topology associated with the first process technology; identifying a first set of physical parameter values associated with first electrical component and the second electrical component of the first sub-circuit; determining a set of performance parameter values for the first sub-circuit based on a first machine learning model of the first sub-circuit and the identified set of physical parameters; converting the identified first sub-circuit to a second sub-circuit for the second process technology based on the determined set of performance parameter values; and outputting the second sub-circuit.

Automated geometry optimization for analog, mixed-signal circuit design

A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed.

Expanded head pillar for bump bonds

A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

Industrial chip scale package for microelectronic device

A microelectronic device has bump bonds and an inductor on a die. The microelectronic device includes first lateral conductors extending along a terminal surface of the die, wherein at least some of the first lateral conductors contact at least some of terminals of the die. The microelectronic device also includes conductive columns on the first lateral conductors, extending perpendicularly from the terminal surface, and second lateral conductors on the conductive columns, opposite from the first lateral conductors, extending laterally in a plane parallel to the terminal surface. A first set of the first lateral conductors, the conductive columns, and the second lateral conductors provide the bump bonds of the microelectronic device. A second set of the first lateral conductors, the conductive columns, and the second lateral conductors are electrically coupled in series to form the inductor. Methods of forming the microelectronic device are also disclosed.

Inductor on microelectronic die

An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas spaced apart from one another along the first direction. The multilevel package substrate includes a conductive structure having first and second ends and conductive portions in the first and second levels that provide a conductive path along the first direction from the landing areas toward the second end, where the conductive structure includes indents that extend into the conductive portions in the first level, the indents spaced apart from one another along the first direction and positioned along the first direction between respective pairs of the landing areas.

Electronic device multilevel package substrate for improved electromigration performance

An example apparatus includes: an integrated circuit including a first surface and terminals; a package including: a housing around the integrated circuit, the housing exposing the first surface; and an electrical interconnect including a second surface and an opening, the second surface electrically coupled to the terminals, the second surface mechanically coupled to the housing, the opening configured to expose the first surface.

Integrated circuit device package

In examples, a sensor package includes a semiconductor die, a sensor on the semiconductor die, and a mold compound covering the semiconductor die. The mold compound includes a sensor cavity over the sensor. The sensor package includes a polymer film member on the sensor and circumscribed by a wall of the mold compound forming the sensor cavity. The polymer film member is exposed to an exterior environment of the sensor package.

Sensor package cavities with polymer films

Multi-algorithmic approach to represent highly non-linear high dimensional space

In a described example, an apparatus includes: a first mold compound partially covering a thermal pad that extends through a pre-molded package substrate formed of a first mold compound, a portion of the thermal pad exposed on a die side surface of the pre-molded package substrate, the pre-molded package substrate having a recess on the die side surface, with an exposed portion of the thermal pad and a portion of the first mold compound in a die mounting area in the recess; a semiconductor die mounted to the thermal pad and another semiconductor die mounted to the mold compound in the die mounting area; wire bonds coupling bond pads on the semiconductor dies to traces on the pre-molded package substrate; and a second mold compound over the die side surface of the pre-molded package substrate and covering the wire bonds, the semiconductor dies, the recess, and a portion of the traces.

Package for power semiconductor devices

A method for interconnecting bond pads of semiconductor dies or devices with corresponding leads in a lead frame with printed conductive interconnects in lieu of bond wires and an apparatus resulting from the above method. More specifically, some examples include printing an insulating foundation path from bond-pads on a semiconductor die to leads of a lead frame to which the semiconductor die is attached. A foundation conductive trace is printed on top of the insulating foundation path from each bond pad on the die to a corresponding lead of the lead frame. Optionally, on top of the conductive trace, a cover insulating cover layer is applied on exposed portions of the conductive interconnects and the foundation insulating layer. Preferably, this can be the same material as foundation layer to fully adhere and blend into a monolithic structure, rather than separate layers. Optionally, a protective layer is then applied on the resulting apparatus.

Printed package and method of making the same

In examples, a sensor package includes a semiconductor die, a sensor on the semiconductor die, and a ring encircling the sensor. The sensor and an inner surface of the ring are exposed to an exterior environment of the sensor package. The sensor package includes a mold compound covering the semiconductor die and abutting an outer surface of the ring.

Miniature sensor cavities

In some examples, a semiconductor package comprises a semiconductor die; an operational component on an active surface of the semiconductor die; and a cover coupled to the active surface of the semiconductor die and covering the operational component. The cover comprises a monolithic structure including a vertical portion and a horizontal portion. A hollow area is between the cover and the operational component. The package also includes a mold compound covering the semiconductor die and the cover.

Covers for semiconductor package components

In one instance, a semiconductor package includes a metal leadframe having a first plurality of openings extending partially into the leadframe from the first side and a second plurality of openings extending partially into the leadframe from the second side together forming a plurality of leads. A pre-mold compound is positioned in the second plurality of openings that at least partially supports the plurality of leads. The semiconductor package has a plurality of bumps extending from the landing sites to a semiconductor die and a molding compounding at least partially covering the plurality of bumps and the metal leadframe. Other packages and methods are disclosed.

Pre-molded leadframes in semiconductor devices

In one instance, a method of forming a semiconductor package with a leadframe includes cutting, such as with a laser, a first side of a metal strip to a depth Daccording to a cutting pattern to form a first plurality of openings, which may be curvilinear. The method further includes etching the second side of the metal strip to a depth Daccording to a photoresist pattern to form a second plurality of openings. At least some of the first plurality of openings are in fluid communication with at least some of the second plurality of openings to form a plurality of leadframe leads. The depth Dis shallower than a height H of the metal strip, and the depth Dis also shallower than the height H. Other embodiments are presented.

Leadframes in semiconductor devices

A microelectronic device includes a die less than 300 microns thick, and an interface tile. Die attach leads on the interface tile are electrically coupled to die terminals on the die through interface bonds. The microelectronic device includes an interposer between the die and the interface tile. Lateral perimeters of the die, the interposer, and the interface tile are aligned with each other. The microelectronic device may be formed by forming the interface bonds and an interposer layer, while the die is part of a wafer and the interface tile is part of an interface lamina. Kerfs are formed through the interface lamina, through the interposer, and partway through the wafer, around a lateral perimeter of the die. Material is subsequently removed at a back surface of the die to the kerfs, so that a thickness of the die is less than 300 microns.

Wafer level bump stack for chip scale package

Growing community of inventors

Allen, TX, United States of America

Sreenivasan Kalyani Koduri