Xilinx, Inc.

Soon-Shin Chee

Paul Ying-Fung Wu

Steven H C Hsieh

Ann Chiuchin Lin

Paul Y Wu

Alelie Funcell

Abhay Maheshwari

A semiconductor device package and methods of manufacturing the same are described. In some examples, a semiconductor device includes an IC die including a ring of die pads around a periphery thereof, lands disposed within the ring of die pads, bond terminals coupled to the lands, the bond terminals being wire-bonded to respective ones of the die pads, and at least one capacitor having respective terminals mounted to respective ones of the lands.

Semiconductor device package and methods of manufacturing the same

A packaged integrated circuit includes an integrated circuit and a package substrate. A trace in the package substrate includes a first portion and a second, high-inductance, portion. The high-inductance portion of the trace is proximate to a port of the integrated circuit and provides a selected inductance operating in cooperation with the capacitance of the port to reduce return loss from the port. The first portion of the trace is part of a transmission line having a characteristic impedance.

Packaged integrated circuit

A method and apparatus is provided to reduce the spreading inductance and increase the distributed capacitance of power planes within the power distribution system of a semiconductor package substrate. In one embodiment, pre-fabricated copper-clad laminate (CCL) structures are utilized as starting material for the power plane pairs, which are then integrated into a package substrate using imaging, lamination, and drilling/plating processes. In alternate embodiments, a starting material having a larger insulating layer thickness may be used to form the CCL structure, whereby a pair of metallic planes having a perforated mesh pattern are adjoined through a dielectric layer to create an effective separation distance between the metallic planes. Alternate embodiments employ plating or deposition methods to obtain a minimum separation distance between the metallic planes of a power plane pair.

Method and apparatus for a power distribution system

A lid having a plurality of recesses at the edges of the lid to provide an improved adhesive bond between the lid and a substrate of an integrated circuit is disclosed. The plurality of recesses may be a castellation comprising a collection of semi-circular cuts into the originally straight edges of the lid. The castellation can be formed by stamping, etching, molding design, or milling/drilling, all of which are well-known methods in the art of forming lids for integrated circuits. The castellation can be vertically straight or it can be slightly tapered, to provide a better locking of the lid on to the package. Epoxy in the recesses can provide an epoxy post for locking the lid. Method of forming a lid having a plurality of recesses and employing a lid on an integrated circuit are also disclosed.

Lid and method of employing a lid on an integrated circuit

A packaged integrated circuit includes an integrated circuit and a package substrate. A trace in the package substrate includes a first portion and a second, high-inductance, portion. The high-inductance portion of the trace is proximate to a port of the integrated circuit and provides a selected inductance operating in cooperation with the capacitance of the port to reduce return loss from the port.

Integrated circuit package with improved return loss

A method of producing a carrier wafer for an integrated circuit is disclosed. The method comprises the steps of providing a carrier wafer having a plurality of bump pads and a plurality of wire bond pads; providing a passivation layer on the carrier wafer; etching a passivation layer over at least a portion of the plurality of bump pads; applying solder bumps on the plurality of bump pads; and separately etching the passivation layer over at least a portion of the plurality of wire bond pads. An integrated circuit employing a flip chip is also disclosed.

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Sunnyvale, CA, United States of America

Soon-Shin Chee