Infineon Technologies Ag

Soon Lock Goh

Swee Kah Lee

Joachim Mahler

Mei Chin Ng

Chau Fatt Chiang

Kok Yau Chua

Beng Keh See

Sook Woon Chan

Jagen Krishnan

Yik Yee Tan

Muhammad Muhammat Sanusi

Hock Heng Chong

Fong Mei Lum

Guan Choon Matthew Nelson Tee

Chew Theng Tai

Aileen Manantan Soriano

Peh Hean Teh

Poh Cheng Lim

Klaus Schiess

Manfred Mengel

Stefan Landau

Henrik Ewe

Reimund Engl

Holger Torwesten

Robert Bergmann

Boris Plikat

Alvin Wee Beng Tatt

Stefan Schmid

Chin Wei Ronnie Tan

A method of manufacturing a package, comprising embedding the semiconductor chip with an encapsulant comprising a transition metal in a concentration in a range between 10 ppm and 10,000 ppm; selectively converting of a part of the transition metal, such that the electrical conductivity of the encapsulant increases; and plating the converted part of the encapsulant with an electrically conductive material.

Manufacturing a package using plateable encapsulant

A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads embedded in the mold compound are electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.

Molded semiconductor package having an optical inspection feature

A package which comprises a first encapsulant configured so that electrically conductive material is plateable thereon, and a second encapsulant configured so that electrically conductive material is not plateable thereon.

Semiconductor package with plateable encapsulant and a method for manufacturing the same

An electronic device comprising a carrier having a mounting surface, at least one electronic chip mounted on the mounting surface, an encapsulant at least partially encapsulating the carrier and the at least one electronic chip, and a plurality of capsules in the encapsulant, wherein the capsules comprise a core comprising an additive and comprise a shell, in particular a crackable shell, enclosing the core.

Embedding additive particles in encapsulant of electronic device

A molded semiconductor package includes a mold compound having opposing first and second main surfaces and an edge extending between the first and second main surfaces. A semiconductor die is embedded in the mold compound. A plurality of metal pads are also embedded in the mold compound and electrically connected to the semiconductor die. The metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound. The metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound. The faces of the metal pads uncovered by the mold compound are plated. The side face of each metal pad disposed around the periphery of the molded package is recessed inward from the edge of the mold compound. A corresponding manufacturing method is also described.

Method of manufacturing molded semiconductor packages having an optical inspection feature

A primer composition is provided. The primer composition includes at least one bi- or multi-functional benzoxazine compound; and at least one compound including a functional group having affinity for a metallic surface, and a cross-linkable group. A method of forming a primer layer on a semiconductor device, and a method of encapsulating a semiconductor device are also provided.

Primer composition, method of forming a primer layer on a semiconductor device, and method of encapsulating a semiconductor device

A semiconductor package includes a plurality of bond pads having a first side and a second side opposing the first side, a coating covering the first side of the bond pads, semiconductor dies and electrical conductors attached to the second side of the bond pads, and a molding compound encasing the semiconductor dies and the electrical conductors at the second side of the bonds pads. The molding compound has a first side through which the bond pads protrude and a second side opposing the first side, the first side of the molding compound having a planar surface between adjacent ones of the bond pads. The package further includes a material plated on exposed sidewalls of the bonds pads uncovered by the molding compound and which is detectable by optical inspection. A corresponding method of manufacture is also provided.

Leadless semiconductor package with optical inspection feature

Embodiments provide a method of forming a chip package. The method may include attaching at least one chip on a carrier, the chip including a plurality of chip pads on a surface of the chip opposite to the carrier; depositing a first adhesion layer on the carrier and on the chip pads of the chip, the first adhesion layer including tin or indium; depositing a second adhesion layer on the first adhesion layer, the second adhesion layer including a silane organic material; and depositing a lamination layer or an encapsulation layer on the second adhesion layer and the chip.

Chip package and method of forming the same

Device and method for an electronic device package is disclosed. The electronic device package includes a first pad, a second pad and an encapsulation surrounding the first and second pad, wherein the encapsulation includes a first opening underneath the first pad and a second opening underneath the second pad. A first bump is arranged in the first opening and a second bump is arranged in the second opening, wherein the encapsulation mechanically locks the first bump to the first pad and the second bump to the second pad.

Method of manufacturing an electronic device with a package locking system

A method for producing a power semiconductor module having surface mountable flat external contact areas is disclosed. At least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the side edges of the semiconductor chip as far as the inner housing plane was a leaving free the source and gate contact areas on the top side of the semiconductor chip and also was partly leaving free the top sides of the corresponding external contacts.

Method for producing a power semiconductor module comprising surface-mountable flat external contacts

A method of manufacturing a semiconductor package with a bump using a carrier. One embodiment provides forming a bump on a carrier. A gap is formed in the carrier that undercuts the bump. A semiconductor chip is attached to the carrier. The chip is electrically connected to the bump. An encapsulant is deposited into the gap. The carrier is removed from the bump.

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Melaka, Malaysia

Soon Lock Goh