Skhynix Inc.

Soo Yeol Chai

Sung Lae Oh

Jong Woo Kim

Kang Woo Park

Jin Haeng Lee

Je Hyun Choi

A page buffer circuit may include: a data transfer circuit configured to transfer data, transferred to a first sensing node through a bit line, to a second sensing node during a data sensing operation; a first latch circuit configured to sense the data transferred to the first sensing node, and store the sensed data; and a second latch circuit configured to sense the data transferred to the second sensing node, and store the sensed data.

Page buffer circuit and operation method thereof

A memory device includes a memory structure and a control circuit. The memory structure includes plural page buffers coupled to non-volatile memory cells. Each non-volatile memory cell is capable of storing data. The plural page buffers are disposed in a predetermined direction. The control circuit is configured to separate reset sections of two page buffers from each other by a time corresponding to at least one of the reset sections. The two page buffers are disposed adjacent to each other among the plural page buffers.

Apparatus and method for reducing signal interference in a semiconductor device

A memory device includes: a plurality of page buffers connected a plurality of bit lines and configured to selectively precharge the bit lines, and a control circuit configured to: perform a first verify operation by applying a precharge voltage to a first bit line among the bit lines according to program data and by applying a first verify voltage to a selected word line, perform a second verify operation, after the first verify operation, by applying the precharge voltage to a second bit line not overlapping the first bit line and by applying a second verify voltage to the selected word line, and perform at least one of an operation of floating the first bit line and an operation of applying the precharge voltage according to a threshold voltage of a memory cell connected to the first bit line during the second verify operation.

Memory device for effectively checking program state and operation method thereof

A memory device may include a plurality of memory cells, a peripheral circuit configured to perform a plurality of program loops on selected memory cells among the plurality of memory cells, each of the plurality of program loops including a program pulse application operation and a program verify operation, and control logic configured to control the peripheral circuit to suspend an nprogram loop (n is a natural number equal to or greater than 1) among the plurality of program loops in response to a suspend command received during the nprogram loop, and to resume the nprogram loop with a negative verify operation in response to a resume command. The negative verify operation applies a negative voltage having a voltage less than a state voltage at the time of application of the resume command.

Memory device and operating method of the memory device including detecting erase cell disturbance during programming

A page buffer includes a bit line controller connected between a bit line and a sensing node, wherein the bit line controller is capable of adjusting a potential level of the sensing node, based on a cell current amount of the bit line, by performing an evaluation operation. The page buffer also includes a first latch unit connected to the sensing node, wherein the first latch unit is capable of adjusting an operation period of the evaluation operation. The page buffer further includes a second latch unit for latching verify data, based on the potential level of the sensing node.

Page buffer comprising a bit line controller and latch units

The present technology provides a method of operating a semiconductor memory device detecting a threshold voltage distribution for memory cells included in a page selected from among a plurality of memory cells. The method of operating the semiconductor memory device includes selecting a target state in which the threshold voltage distribution is to be detected, determining a plurality of read voltages for dividing a voltage range in which a threshold voltage of the selected target state is distributed, and performing a plurality of sensing operations using the plurality of read voltages on the selected page. Masking to the target state is applied in each of the plurality of sensing operations.

Semiconductor memory device and method of operating the semiconductor memory device

A memory device includes a cell wafer having a first pad on one surface thereof; and a peripheral wafer bonded to the one surface of the cell wafer, and having a second pad coupled to the first pad. The cell wafer includes a memory cell array; first and second bit lines coupled to the memory cell array; and a bit line selection circuit configured to couple one of the first and second bit lines to the first pad. The peripheral wafer includes a page buffer low-voltage circuit including a first page buffer low-voltage unit corresponding to the first bit line and a second page buffer low-voltage unit corresponding to the second bit line; and a page buffer high-voltage circuit configured to couple one of the first and second page buffer low-voltage units to the second pad.

Memory device having wafer-to-wafer bonding structure

Provided herein may be a memory device having a page buffer. The memory device may include a memory cell configured to store data, and a page buffer coupled to the memory cell through a bit line and configured to store data to be used in a program operation and to precharge the bit line to a first precharge voltage or a second precharge voltage lower than the first precharge voltage depending on the data during a program verify operation performed in the program operation.

Memory device having page buffer

Provided herein is a memory device and a method of operating the same. The memory device may include a memory block including a plurality of memory cells, and a peripheral circuit configured to apply a plurality of operating voltages to a plurality of word lines of the memory block during a program operation, wherein, during a verify operation included in the program operation, the peripheral circuit may be configured to allow a selected word line, among the plurality of word lines, to float, and may decrease a potential of the selected word line to a pre-level by decreasing potentials of adjacent word lines to the selected word line.

Memory device and method of applying operating voltage

The present technology includes a memory device. The memory device includes memory cells, page buffers configured to store sensed data obtained from the memory cells, a current sensing circuit configured to compare a sensed voltage generated according to the sensed data and a reference voltage generated according to an allowable fail bit code, and output a pass signal or a fail signal according to a comparison result, and a fail bit manager configured to increase an allowable number of fail bits included in the allowable fail bit code until the pass signal is output from the current sensing circuit, change the allowable fail bit code according to the allowable number of fail bits, and provide the allowable fail bit code to the current sensing circuit.

Memory device for counting fail bits included in sensed data

Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell array including a plurality of memory cells, a peripheral circuit configured to program the plurality of memory cells to a plurality of program states, and a control logic configured to control the peripheral circuit so that program operations corresponding to the plurality of program states are performed, wherein the control logic controls the peripheral circuit so that, during a program operation for a target program state, among the plurality of program states, memory cells to be programmed to an immediately higher program state than the target program state are programmed to the target program state.

Memory device having a control logic to control program operations and method of operating the same

The present technology relates to an electronic device. A memory device capable of reducing a time consumed in a program operation includes a memory cell array, a page buffer group connected to the memory cell array through a plurality of bit lines and a voltage generator configured to generate voltages to apply to each of a plurality of page buffers included in the page buffer group. Each of the plurality of page buffers includes a precharge circuit that controls potential levels of the plurality of bit lines to be maintained at precharge levels.

Memory device for controlling voltage of bit line and method of operating the same

The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a first latch circuit configured to store data corresponding to one of a first program state and a second program state, a bit line controller connected to a bit line of a memory block and precharging the bit line by applying one of a first set voltage and a second set voltage to the bit line according to the data stored in the first latch circuit during a bit line precharge operation in a program verify operation, and a second latch circuit connected to the bit line controller through a main sensing node and configured to sense first verify data according to a potential level of the main sensing node during the program verify operation.

Page buffer and semiconductor memory device having the page buffer

There are provided a memory device and an operating method thereof. The memory device includes memory cells connected between a bit line and a source line, a voltage generator for generating program voltages and verify voltages which are to be applied to a selected word line connected to a selected memory cell, a page buffer for storing data respectively sensed in verify operations using the verify voltages, and for transferring a program allow voltage, a program inhibit voltage or a program control voltage to the bit line by sequentially using the data, and a logic circuit for generating page buffer control signals for controlling the page buffer.

Memory device for forming narrow threshold voltage distribution and operating method thereof

A group control circuit includes a selection signal generation circuit and first and second activation selection circuits. The selection signal generation circuit generates a source selection signal by synchronizing an entry control signal. The first activation selection circuit generates a plurality of first activation selection signals in synchronization with a first edge clock signal. The second activation selection circuit generates a plurality of second activation selection signals in synchronization with a second edge clock signal. The first and second activation selection circuits have a parallel structure.

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Gyeonggi-do, South Korea

Soo Yeol Chai