Stats Chippac Pte. Ltd.

Soo Won Lee

Jeffrey David Punzalan

Byung Tai Do

KyungOe Kim

SeungYong Chai

Bartholomew Liao Chung Foh

Dao Nguyen Phu Cuong

Kyung Moon Kim

Kwok Keung Szeto

Zigmund Ramirez Camacho

Lionel Chien Hui Tay

Jong-Woo Ha

Jairus Legaspi Pisigan

Koo Hong Lee

JiHoon Oh

JuHyun Park

Sung Jun Yoon

Kyu Won Lee

Eun Jin Jeong

An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.

Integrated circuit packaging system with substrate and method of manufacture thereof

A semiconductor device has a substrate. A conductive layer is formed over the substrate. A duplex plated bump on lead pad is formed over the substrate. An insulating layer is formed over the conductive layer and the substrate. A portion of the insulating over the duplex plated bump on lead pad is removed using a laser direct ablation process. The insulating layer is a lamination layer. The duplex plated bump on lead pad has a wide bump on lead pad. A semiconductor die is mounted over the substrate. The semiconductor die has a composite conductive interconnect structure. The semiconductor die has a first bump and a second bump with a pitch ranging from 90-150 micrometers between the first bump and the second bump. A duplex plated contact pad is formed on a surface of the substrate opposite the duplex plated bump-on-lead pad.

Semiconductor device and method of forming duplex plated bump-on-lead pad over substrate for finer pitch between adjacent traces

A method of manufacture of an integrated circuit packaging system includes: providing a carrier having a contact pad; forming a first resist layer, having a first resist opening, over the carrier and the contact pad, the first resist opening partially exposing the first contact pad; forming a second resist layer, having a second resist opening over the first resist opening, the second resist opening partially exposing the first resist layer; mounting an integrated circuit over the carrier; and forming an internal interconnect between the integrated circuit and the carrier, the internal interconnect filling the second resist opening with no space between the second resist layer in the second resist opening.

Integrated circuit packaging system with interconnects and method of manufacture thereof

An integrated circuit packaging system including: forming a base structure, having an opening; mounting a base structure device in the opening; attaching an integrated circuit device over the base structure device; and molding an encapsulant on the base structure, the base structure device, and the integrated circuit device.

Integrated circuit packaging system with base structure device

Growing community of inventors

Yongin-si, South Korea

Soo Won Lee