Seagate Technology Incorporated

Other

Song Sheng Xue

Haiwen Xi

Patrick Joseph Ryan

Kaizhong Gao

Dimitar Velikov Dimitrov

Paul E Anderson

Shaoping Li

Insik Jin

Michael Xuefei Tang

Zheng Gao

Hongyue Liu

Nurul Amin

Dexin Wang

Yang Li

Shuiyuan Huang

Sining Mao

Antoine Khoueir

Qing I He

James F Dolejsi

Michael C Kautzky

Yong Lu

Harry Hongyue Liu

Konstantin Nikolaev

Xuefei Tang

Yiran Chen

Eric Walter Singleton

Hai Li

Mark Thomas Kief

Eric Leroy Granstrom

Steven Kalderon

Yiming Shi

Ming Sun

Xuguang Alan Wang

Yuming Zhou

Wayne Allen Bonin

Wei Tian

Hans L Leuthold

Olle Gunnar Heinonen

Xiaohua Lou

Dadi Setiadi

Housan Dakroub

John Robert Pendray

Jae-Young Yi

Eric Shane Linville

Andrew D White

Bradley Jay Ver Meer

Brian William Karr

Daniel Seymour Reed

Roger L Hipwell

Jeffery K Berkowitz

Kristin Joy Duxstad

Chunhong Hou

Eileen Yan

Khuong T Tran

Matt Johnson

Bryan K Oliver

Yi X Li

Lei Wang

Xiaobin Wang

Jason Charles Jury

Dian Song

Hong Ying Wang

Michael B Hintz

Ibro Tabakovic

Andreas Karl Roelofs

Yizhang Yang

Xilin Peng

Johannes Van Ek

Feng Y Wang

Mallika Kamarajugadda

Janusz Josef Nowak

David James Larson

Juan Jose Fernandez-de-Castro

Alan Biggar Johnston

Daniel John Brown

Markus Siegert

Bradley Hugh Miller

Juren Ding

Bogdan M Simion

Michael R Montemorra

Jeffrey Howard Lake

Rick Michel

Picheng Huang

Mike Montemorra

Alan B Johnston

Mallika Roy

Jian X Shen

Jin Insik

Nural Amin

Laura C Stearns

Horng-Shiong Shawn Chen

Juan Fernandez-deCastro

Paul Edward Anserson

Yon Lu

Jun Ouyang

William Bruce Fitzpatrick

Paul Anderson

A magnetic sensor assembly includes first and second shields each comprised of a magnetic material. The first and second shields define a physical shield-to-shield spacing. A sensor stack is disposed between the first and second shields and includes a seed layer adjacent the first shield, a cap layer adjacent the second shield, and a magnetic sensor between the seed layer and the cap layer. At least a portion of the seed layer and/or the cap layer comprises a magnetic material to provide an effective shield-to-shield spacing of the magnetic sensor assembly that is less than the physical shield-to-shield spacing.

Method for fabricating a magnetic sensor assembly

Magnetic sensing device with reduced shield-to-shield spacing

A method of producing bit-patterned media is provided whereby a shell structure is added on a bit-patterned media dot. The shell may be an antiferromagnetic material that will help stabilize the magnetization configuration at the remanent state due to exchange coupling between the dot and its shell. Therefore, this approach also improves the thermal stability of the media dot and helps each individual media dot maintain a single domain state.

Method of manufacturing magnetic dots

A free ferromagnetic data storage layer of an MRAM cell is coupled to a free ferromagnetic stabilization layer, which stabilization layer is directly electrically coupled to a contact electrode, on one side, and is separated from the free ferromagnetic data storage layer, on an opposite side, by a spacer layer. The spacer layer provides for the coupling between the two free layers, which coupling is one of: a ferromagnetic coupling and an antiferromagnetic coupling.

MRAM cells including coupled free ferromagnetic layers for stabilization

Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region; and a gate stack structure over the substrate and between the source region and drain region. The gate stack structure includes a first solid electrolyte cell and a second solid electrolyte cell. The solid electrolyte cells having a capacitance that is controllable between at least two states. A gate contact layer is electrically coupled to a voltage source. The first solid electrolyte cell and the second solid electrolyte cell separate the gate contact layer from the substrate.

Non-volatile multi-bit memory with programmable capacitance

A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.

Memory with separate read and write paths

Spin torque magnetic memory elements that have a pinned layer, two free layers, and a current-blocking insulating layer proximate to at least one of the free layers. The resistive state (e.g., low resistance or high resistance) of the memory elements is altered by passing electric current through the element in one direction. In other words, to change from a low resistance to a high resistance, the direction of electric current is the same as to change from a high resistance to a low resistance. The elements have a unidirectional write scheme.

Spin-torque memory with unidirectional write scheme

A magnetic junction memory array and methods of using the same are described. The magnetic junction memory array includes a plurality of electrically conductive word lines extending in a first direction, a plurality of electrically conductive bit lines extending in a second direction and forming a cross-point array with the plurality of electrically conductive word lines, and a memory cell proximate to, at least selected, cross-points forming a magnetic junction memory array. Each memory cell includes a magnetic pinned layer electrically between a magnetic bit and an isolation transistor. The isolation transistor has a current source and a gate. The current source is electrically coupled to the cross-point bit line and the gate is electrically coupled to the cross-point word line. An electrically conductive cover layer is disposed on and in electrical communication with the magnetic bits.

Write-once magentic junction memory array

Write verify methods for resistance random access memory (RRAM) are provided. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state and applying a forward resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance value less than a selected lower resistance limit value. The method also includes applying a reverse resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance values is greater than a selected upper resistance limit value. The reverse resetting voltage pulse has a second polarity being opposite the first polarity.

Write verify method for resistive random access memory

A magnetoresistive device includes a free layer, a separating layer, a pinned layer, and a magnetic stabilizer in close proximity to the pinned layer, wherein the magnetic stabilizer may enhance the stability of the magnetization direction of the pinned layer.

Magnetoresistive device with enhanced pinned layer

A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.

MRAM diode array and access method

A transistor device includes a magnetic field source adapted to deflect a flow of free electron carriers within a channel of the device, between a source region and a drain region thereof. According to preferred configurations, the magnetic field source includes a magnetic material layer extending over a side of the channel that is opposite a gate electrode of the transistor device.

Magnet-assisted transistor devices

Bit-patterned stack with antiferromagnetic shell

Magnetic tunnel junction cells and methods of making magnetic tunnel junction cells that include a radially protective layer extending proximate at least the ferromagnetic free layer of the cell. The radially protective layer can be specifically chosen in thickness, deposition method, material composition, and/or extent along the cell layers to enhance the effective magnetic properties of the free layer, including the effective coercivity, effective magnetic anisotropy, effective dispersion in magnetic moment, or effective spin polarization.

Memory cell with radial barrier

A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.

Growing community of inventors

Edina, MN, United States of America

Song Sheng Xue