International Business Machines Corporation

Applied Materials, Inc.

Hitachi Global Storage Technologies Netherlands B.v.

Globalfoundries Inc.

Adeia Semiconductor Bonding Technologies Inc.

Other

Sony Corporation

Lam Research Corporation

Siemens Aktiengesellschaft

Samsung Electronics Co., Ltd.

Advanced Micro Devices Corporation

Sony Electronics Inc

Chartered Semiconductor Manufacturing Ltd (corporation)

Sienens Aktiengesellschaft

Son Van Nguyen

Alfred Grill

Deepika Priyadarshini

Hosadurga K Shobha

Takeshi Nogami

Stephen McConnell Gates

Daniel C Edelstein

Donald Francis Canaperi

Sanjay C Mehta

Richard Hsiao

Deborah A Neumayer

Griselda Bonilla

Quang Le

David M Dobuzinsky

Satyanarayana Venkata Nitta

Li-Qun Xia

Christopher J Penny

Elbert Emin Huang

Thomas M Shaw

Richard Anthony Conti

Chih-Chao Yang

Jeffrey P Gambino

Vamsi Krishna Paruchuri

Vishnubhai Vitthalbhai Patel

Kangguo Cheng

Juntao Li

Chanro Park

Robert Dennis Miller

Shankar Venkataraman

Xiao Hu Liu

Christos Dimitrios Dimitrakopoulos

Denny Tang

Tenko Yamashita

Shom Ponoth

Jeffrey Scott Lille

Tue H Nguyen

Edward Hin Pong Lee

Michael Rizzolo

Cherngye Hwang

Christopher Joseph Waskiewicz

Wei Lin

Michael Jay Shapiro

Alexander Reznicek

Jack Allan Mandelman

David V Horak

William R Tonti

Toshiharu Furukawa

Mustafa Pinarbasi

Dureseti Chidambarrao

Balasubramanian Pranatharthiharan

Benjamin David Briggs

Rudy J Wojtecki

Qinghuang Lin

Vladimir Nikitin

Su Chen Fan

Pai-Hung Pan

Joshua M Rubin

Eric R Miller

Ashim Dutta

Vincent James McGahay

Murali Ramasubramanian

Mihaela A Balseanu

Cornelius Brown Peethala

Reinhard J Stengl

Shyng-Tsong Chen

Xinhui Wang

David Robert Medeiros

Kaushik Chanda

Ruilong Xie

Lawrence Alfred Clevenger

Brent A Anderson

Theodorus E Standaert

Shogo Mochizuki

Vijay Narayanan

Srinivas D Nemani

Ruqiang Bao

Ellie Y Yieh

Jingyun Zhang

Katherine Lynn Saenger

Robert Fontana

Martin Michael Frank

Yann Mignot

Mehul B Naik

Jae Hun Kim

Kuok San Ho

Kisik Choi

Jeffrey Childress

Bomy A Chen

Nicholas Anthony Lanzillo

Aron Pentek

Terry Allen Spooner

Neil Leslie Robertson

Gary Bela Bronner

Muthumanickam Sankarapandian

Bok Hoen Kim

Hichem M'Saad

Ching Hwa Tsang

John Christopher Arnold

David Edward Kotecki

Girish Anant Dixit

A semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is positioned on top of the first transistor. A second gate is electrically coupled to the second transistor. A dielectric isolation layer is positioned between the first gate and the second gate. A first conductive contact is electrically coupled to the first gate. A second conductive contact is electrically coupled to the second gate. A control of the first gate through the first conductive contact is independent of a control of the second gate through the second conductive contact.

Stacked field effect transistor structure with independent gate control between top and bottom gates

A first BEOL layer, including a first and a second signal line, a conformal dielectric surrounding an upper portion of a vertical sidewall of each of the first signal line and the second signal line, an air gap between the first and the second signal line, a vertical side boundary of the air gap is a vertical side surface of the first signal line. Forming a first and a second metal line in a sacrificial material in a first BEOL layer, removing the sacrificial material, forming a conformal dielectric surrounding vertical side surfaces of the first and the second metal line, an air gap between the first and the second metal line exposes an upper horizontal surface of a dielectric layer below the first BEOL layer, growing a dielectric selectively from an upper portion of the conformal dielectric, the air gap remains between the first and the second metal line.

Air gap in beol interconnect

A semiconductor device includes a field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extend vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region includes a conduit liner and an inner column internal to the conduit liner that extends below a bottom surface of the wraparound gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.

Field effect transistor with backside source/drain

Embodiments of the invention provide self-assembled monolayers (SAM) formulations and cleaning to promote quick depositions. A hydrogen-based plasma clean is performed on a structure, the structure including a metal layer and a dielectric layer. A self-assembled monolayers (SAM) solution is dispensed on the structure, the SAM solution including SAMs and a solvent, the SAMs being configured to assemble on the metal layer. The structure is rinsed with a rinse solution including the solvent.

Sam formulations and cleaning to promote quick depositions

A semiconductor structure including a first dielectric layer comprising a first conductive metal feature embedded in the first dielectric layer; and a second dielectric layer including a second conductive metal feature embedded in the second dielectric layer, the second conductive metal feature is above and directly contacts the first conductive metal feature, and an interface between the second conductive metal feature and the second dielectric layer includes a repeating scallop shape along its entire length.

Semiconductor structure having alternating selective metal and dielectric layers

A semiconductor fabrication method that uses a graphene etch stop is disclosed. The method comprises forming a first set of trenches and a second set of trenches in a substrate. The first set of trenches are narrower than the second set of trenches. The method further comprises forming a graphene layer in the first and second sets of trenches. The method further comprises depositing a first conductor in the first and second sets of trenches. The method further comprises removing the first conductor from the second set of trenches using an etching process. The graphene layer acts as an etch stop for the etching process. The method further comprises depositing a second conductor in the second set of trenches. The second conductor is different than the first conductor.

Composite interconnect formation using graphene

Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Method of forming copper interconnect structure with manganese barrier layer

A method of making a semiconductor device includes forming a gate stack on a substrate. The method further includes depositing a first spacer layer on a sidewall of the gate stack. The first spacer layer includes silicon and carbon. The method includes performing a first nitrogen plasma treatment process on the first spacer layer to increase a density of the first spacer layer. The method further includes depositing a second spacer layer on the first spacer layer. The second spacer layer includes silicon, carbon, and nitrogen.

Nano multilayer carbon-rich low-k spacer

A method of fabricating a dielectric film includes depositing a first precursor on a substrate. The first precursor includes a cyclic carbosiloxane group comprising a six-membered ring. The method also includes depositing a second precursor on the substrate. The first precursor and the second precursor form a preliminary film on the substrate, and the second precursor includes silicon, carbon, and hydrogen. The method further includes exposing the preliminary film to energy from an energy source to form a porous dielectric film.

Forming high carbon content flowable dielectric film with low processing damage

Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

Air gap spacer formation for nano-scale semiconductor devices

Copper interconnect structure with manganese barrier layer

A deposition apparatus for depositing a material on a substrate is provided. The deposition apparatus has a processing chamber defining a processing space in which the substrate is arranged, an ultraviolet radiation assembly configured to emit ultraviolet radiation and a microwave radiation assembly configured to emit microwave radiation into an excitation space that can be the same as the processing space, and a gas feed assembly configured to feed a precursor gas into the processing space and a reactive gas into the excitation space. The ultraviolet radiation assembly and the microwave radiation assembly are operated in combination to excite the reactive gas in the excitation space. The material is deposited on the substrate from the reaction of the excited reactive gas and the precursor gas. A method for using the deposition apparatus to deposit a material on a substrate is provided.

Microwave plasma and ultraviolet assisted deposition apparatus and method for material deposition using the same

Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.

Ultrathin multilayer metal alloy liner for nano Cu interconnects

A method is presented for forming a fully aligned via (FAV) structure. The method includes depositing a first dielectric adjacent a conductive material, forming a surface aligned monolayer (SAM) over the conductive material, the SAM defining a long chain SAM formed by a layer-by-layer growth technique, depositing a second dielectric over the SAM and the first dielectric, performing chemical mechanical polishing (CMP) to planarize the second dielectric, and etching the SAM to form the FAV structure.

Selective deposition with SAM for fully aligned via

A method includes forming a metallic interconnect structure on a semiconductor substrate where the metallic interconnect structure comprises a plurality of metal lines with adjacent metal lines separated by a gap therebetween. The method further includes selectively depositing a first low-k dielectric material onto the semiconductor substrate and onto exposed surfaces of the metal lines of the metallic interconnect structure to form a barrier on at least the metal lines. The barrier is configured to minimize oxidation and diffusion of metal of the metal lines. The method also includes depositing a flowable second low-k dielectric material onto the semiconductor substrate to form a dielectric layer encapsulating the barrier and the metallic interconnect structure.

Metallic interconnect structure

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Schenectady, NY, United States of America

Son Van Nguyen