Kabushiki Kaisha Toshiba

Nikon Corporation

Shin-etsu Handotai Co., Ltd.

Toshiba Memory Corporation

Dai Nippon Printing Co., Ltd.

Soichi Inoue

Satoshi Tanaka

Toshiya Kotani

Tadahito Fujisawa

Koji Hashimoto

Shinichi Ito

Shoji Mimotogi

Takashi Sato

Kazuko Yamamoto

Kenji Kawano

Shigeki Nojima

Ichiro Mori

Kazuya Fukuhara

Suigen Kyoh

Kyoko Izuha

Iwao Higashikawa

Keiji Horioka

Kazuhiro Takahata

Kei Yoshikawa

Kazuya Sato

Masafumi Asano

Hiroko Nakamura

Shinji Yamaguchi

Shigehiro Hara

Akiko Mimotogi

Yoji Ogawa

Katsuya Okumura

Hiroyuki Sato

Tsuneyuki Hagiwara

Kazuyoshi Sugihara

Shuichi Tamamushi

Tatsuhiko Higashiki

Shingo Kanamitsu

Hideki Kanai

Makoto Kobayashi

Sachiko Kobayashi

Kenichi Kodama

Shin-ichi Ito

Takayuki Iwamatsu

Masashi Ichikawa

Hideya Miyazaki

Seiji Morita

Haruo Okano

Masamitsu Itoh

Yuichiro Yamazaki

Motosuke Miyoshi

Takahiro Ikeda

Toru Watanabe

Masami Aoki

Kei Hayasaki

Kiyomi Koyama

Osamu Ikenaga

Haruki Komano

Shigeru Hasebe

Tadahiro Takigawa

Mari Inoue

Takumichi Sutani

Sachiko Miyama

Mitsuyo Kariya

Ryoichi Suzuki

Shinji Sato

Yusuke Kohyama

Hisashi Kaneko

Takashi Sakamoto

Takamasa Usui

Masahiko Hasunuma

Masanori Takahashi

Ikuo Yoneda

Hiroshi Nomura

Yasunobu Onishi

Satoshi Usui

Nobuhiro Komine

Kentaro Matsunaga

Isahiro Hasegawa

Koichi Matsuno

Ryosuke Yamamoto

Kenji Yoshida

Shunko Magoshi

Kazuyuki Masukawa

Kei Hattori

Yasunobu Kai

Shimon Maeda

Takashi Hirano

Hidefumi Mukai

Ryuji Ogawa

Hirotaka Ichikawa

Hisako Aoyama

Masahiro Miyairi

Takeharu Motokawa

Tetsuaki Matsunawa

Tsuyoshi Shibata

Ryuichi Saito

Mitsuyo Asano

Michiya Takimoto

Hirotaka Ichiakwa

Takamasa Takaki

Akiko Nikki

A pattern-forming method includes forming a first film above a material to be processed, processing the first film into a pattern to be formed in the material to be processed, providing a second film on the first film and the material to be processed, supplying a precursor containing at least one of a metal material or a semiconductor material to the second film, removing the first film, and processing the material to be processed using the second film impregnated with at least one of the metal material and the semiconductor material, as a mask.

Pattern-forming method

A semiconductor memory device includes a stacked body including a first electrode layer and a second electrode layer stacked on the first electrode layer, and first and second interconnections on a first surface of the stacked body. The first and second electrode layers have first and second end surfaces respectively in the first surface. The first interconnection is electrically connected to the first electrode layer through a first region of the first end surface; and the second interconnection is electrically connected to the second electrode layer through a second region of the second end surface. The first and second interconnections extend in a first direction on the first surface. The first and second regions are arranged in a second direction crossing the first direction with a crossing angle smaller than 90 degrees. The first region and the second region each have a boundary along the second direction.

Semiconductor memory device and method for manufacturing same

According to the pattern shape determining method of the embodiment, a first reference position of a pattern shape is set on a first pattern and a second reference position of a pattern shape is set on a second pattern. Moreover, an allowable dimensional difference between the first pattern and the second pattern is set to a value corresponding to a distance from the first reference position. Then, it is determined whether the second pattern has a pattern shape identical with the first pattern, based on whether a dimensional difference between the first pattern and the second pattern is within a range of an allowable dimensional difference set at a position at which the dimensional difference is calculated.

Pattern shape determining method, pattern shape verifying method, and pattern correcting method

According to one embodiment, on a substrate, a resist layer is laminated on an upper side of a pattern formation layer on which a desired pattern is formed. A diffraction pattern that diffracts exposure light irradiated on the substrate is formed further on the upper side than the resist layer. Overall exposure is performed from above the diffraction pattern using a deformed light having illumination light source shape determined according to the desired pattern. Diffracted light diffracted on the diffraction pattern by the exposure is irradiated on the resist layer.

Exposing method and method of manufacturing semiconductor device

According to one embodiment, a deviation amount distribution of a two-dimensional shape parameter between a mask pattern formed on a mask and a desired mask pattern is acquired as a mask pattern map. Such that a deviation amount of the two-dimensional shape parameter between a pattern on substrate formed when the mask is subjected to exposure shot to form a pattern on a substrate and a desired pattern on substrate fits within a predetermined range, an exposure is determined for each position in the exposure shot in forming the pattern on substrate based on the mask pattern map.

Exposure determining method, method of manufacturing semiconductor device, and computer program product

A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.

Method for making a design layout of a semiconductor integrated circuit

A graph in which patterns are each regarded as nodes and nodes of patterns adjacent to each other at a first distance are connected with each other by an edge is produced, each of the patterns is classified into two types so that the two patterns corresponding to the nodes at both ends of the edge are types different to each other, a classification result is corrected by grouping the patterns in each node cluster connected by the edge or each node cluster connected via the node by the edge, and by inverting each of types of a pattern belonging to a same group as that of one pattern, out of a pair of patterns that are classified into a same type and that belong to respectively different groups adjacent to each other at a second distance, and a pattern layout diagram is created based on the corrected classification result.

Pattern layout creation method, program product, and semiconductor device manufacturing method

A resist pattern () is formed in a dimension of a limitation of an exposure resolution over a hard mask material film () over a work film (). The material film () is processed using the resist pattern () as a mask. A hard mask pattern () is thereby formed. Thereby a resist pattern (), over a non-selected region (), having an opening () through which a selection region () in the mask pattern is exposed is formed. Only the mask pattern () exposed through the opening () is slimmed by performing a selection etching, the work film () is etched by using the mask pattern (). A work film pattern () is thereby formed, which include a wide pattern section () of a dimension width of the limitation of the exposure resolution and a slimmed pattern section () of a dimension that is not more than the limitation of the exposure resolution.

Semiconductor device fabrication method using multiple mask patterns

Semiconductor device fabrication method and semiconductor device

Semiconductor device fabrication method using multiple resist patterns

A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.

Mask pattern correcting method, mask pattern inspecting method, photo mask manufacturing method, and semiconductor device manufacturing method

A mask pattern verifying method include obtaining first information about a hot spot from design data of a mask pattern, obtaining second information about the mask pattern actually formed on a photo mask, and determining a measuring spot of the mask pattern actually formed on the photo mask, based on the first and second information.

Mask pattern verifying method

A pattern management method includes extracting patterns having process margins equal to or below a predetermined value from a chip layout of an integrated circuit, screening a plurality of types of representative patterns from the extracted pattern, extracting patterns closest to the most outer periphery of the chip from the representative patterns, and representatively managing the extracted patterns which is closest to the most outer periphery of the chip.

Pattern management method and pattern management program

A computer implemented method for correcting a mask pattern includes: predicting a displacement of a device pattern by using a mask pattern to form the device pattern and a variation of a process condition; determinating an optical proximity correction value so that the displacement falls within a displacement tolerance of the device pattern; and correcting the mask pattern using the optical proximity correction value.

Method for correcting a mask pattern, system for correcting a mask pattern, program, method for manufacturing a photomask and method for manufacturing a semiconductor device

Disclosed is a method of producing a pattern for a semiconductor device, comprising extracting part of a pattern layout, perturbing a pattern included in the part of the pattern layout to generate a perturbation pattern, correcting the perturbation pattern, predicting a first pattern, to be formed on a wafer, from the corrected perturbation pattern, acquiring a first difference between the perturbation pattern and the first pattern, and storing information concerning the perturbation pattern including information concerning the first difference.

Pattern-producing method for semiconductor device

Growing community of inventors

Yokohama, Japan

Soichi Inoue