Globalfoundries Inc.

International Business Machines Corporation

Samsung Electronics Co., Ltd.

Freescale Semiconductor,inc.

Globalfoundries Singapore Pte. Ltd.

Sohan Singh Mehta

Sunil Kumar Singh

Ravi Prakash Srivastava

Daniel A Corliss

Catherine B Labelle

Matthew Thomas Herrick

Vikrant Kumar Chauhan

Norman Chen

Yuyang Sun

SherJang Singh

Shyam Pal

Mark Kelling

Jeong Soo Kim

Craig D Higgins

Feng Wang

Hyung-Rae Lee

Dong Hee Yu

Niall Shepherd

Tong Qing Chen

Vineet Sharma

Methods of lithographic patterning to form interconnect structures for a chip. A hardmask layer is formed on a dielectric layer. A sacrificial layer is formed on the hardmask layer. First opening and second openings are formed in the sacrificial layer that extend through the sacrificial layer to the hardmask layer. A resist layer is formed on the sacrificial layer. An opening is formed in the resist layer that is laterally located between the first opening in the first sacrificial layer and the second opening in the first sacrificial layer. The resist layer is comprised of a metal oxide resist material that is removable selective to the hardmask layer.

Lithographic patterning to form fine pitch features

A litho-litho-etch double patterning method including forming a resist layer by coating a substrate with a resist composition; exposing the resist layer to a first radiant energy density of UV rays; forming a first pattern in the resist layer by developing the resist layer with a positive developer; exposing the resist layer to a second radiant energy density of UV rays; and forming a second pattern in the resist layer by developing the resist layer with a negative developer, the second pattern including one or more features of the first pattern.

Litho-litho-etch double patterning method

Back end of line via formation for semiconductor devices and methods of fabricating the semiconductor devices. One method includes, for instance: obtaining a wafer with a substrate and at least one contact in the substrate; depositing at least one lithography stack over the substrate; performing lithography to pattern at least one via opening; depositing a block co-polymer coating over the wafer into the at least one via opening; performing an ashing to remove excess block co-polymer material and form block co-polymer caps; and performing a thermal bake to separate the block co-polymer caps into a first material and a second material. An intermediate semiconductor device is also disclosed.

Methods and devices for back end of line via formation

Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.

Method for fabricating a semiconductor integrated circuit with a litho-etch, litho-etch process for etching trenches

An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.

Critical dimension and pattern recognition structures for devices manufactured using double patterning techniques

A system and method are provided for automatic dose-correction recipe generation, the system including a dose-correction recipe generator, a reticle data unit in signal communication with the recipe generator, a slit data unit in signal communication with the recipe generator, a process data unit in signal communication with the recipe generator, a wafer data unit in signal communication with the recipe generator, a control unit in signal communication with the recipe generator, and an output unit or a storage unit in signal communication with the control unit; and the method including receiving a current reticle data set and a previous reticle data set, receiving a current slit data set and a previous slit data set, receiving a process condition, receiving a wafer condition, automatically generating a dose-correction recipe in accordance with the received reticle, slit, process and wafer information, and controlling a dose in accordance with the generated recipe.

Semiconductor intra-field dose correction

Growing community of inventors

Saratoga Springs, NY, United States of America

Sohan Singh Mehta