Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Inc.

National University of Singapore

Soh Yun Siah

Juan Boon Tan

Eng Hua Lim

Chong Wee Lim

Chun Hui Low

Kong Hean Lee

Wanbing Yi

Danny Pak-Chum Shum

Alex See

Jia Zhen Zheng

Curtis Chun-I Hsieh

Fan Zhang

Yeow Kheng Lim

Chew Hoe Ang

Liang Choo Hsia

Kin Leong Pey

Hai Cong

Yu Jau Chen

Siow Lee Chwa

Shunqiang Gong

Huajun Liu

Daxiang Wang

Yoke Leng Lim

Pei Ching Lee

Haifeng Sheng

Hyunwoo Yang

Yanxia Shao

Young Seon You

Shyue Seng Tan

Lap Chan

Wei Liu

Simon Yew-Meng Chooi

Huang Liu

Bin Liu

Dimitri Houssameddine

Xinshu Cai

Tze Ho Simon Chan

Pinghui Li

Chenchen Jacob Wang

Mahesh Bhatkar

Liang Li

Wei Shao

Laiqiang Luo

Zhiqiang Teo

Pey Kin Leong

Shifeng Zhao

Yu Jin Eugene Kong

Shao Ning Yuan

Xue Song Rao

Peng Zhou

Kong-Hean Lee

Eng Hwa Lim

A memory device with a dielectric blocking layer for improving interpoly dielectric breakdown is provided. Embodiments include.

Memory device with dielectric blocking layer for improving interpoly dielectric breakdown

The present disclosure relates to split gate flash MLC based neuromorphic processing and method of making the same. Embodiments include MLC split-gate flash memory formed over a substrate, the MLC split-gate flash memory embedded with artificial neuromorphic processing to dynamically program and erase each cell of the MLC split-gate flash memory; and sense visual imagery by the artificial neuromorphic processing.

Neuromorphic memories with split gate flash multi-level cell and method of making the same

Devices and methods of forming a device. A two-terminal device element includes a device stack coupled between first and second terminals. The first terminal contacts a metal line in an underlying interconnect level, and the second terminal is formed over the device layer. An encapsulation liner covers exposed side surfaces of the device stack of the two-terminal device element. A dual damascene interconnect is coupled to the two-terminal device element.

Integrated two-terminal device with logic device for embedded application

Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the dual damascene interconnect in the second region is coupled to the two-terminal device element.

One illustrative integrated circuit (IC) product disclosed herein includes an MRAM cell, the MRAM cell having an outer perimeter, wherein the MRAM cell comprises a bottom electrode, a top electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the IC product also includes an insulating material positioned around the outer perimeter of the MRAM cell and a conductive sidewall spacer comprised of a metal-containing shielding material positioned around the outer perimeter of the MRAM cell, wherein the insulating material is positioned between the conductive sidewall spacer and the MRAM cell.

Shielded MRAM cell

A method of forming a memory device with a dielectric blocking layer and selective silicidation and the resulting device are provided. Embodiments include forming a memory stack on a substrate; forming a conformal insulating layer over sidewalls and an upper surface of the memory stack and the substrate; forming an interpoly dielectric structure adjacent to each sidewall of the insulating layer; forming a conformal polysilicon silicon layer over the insulating layer and interpoly dielectric structures; forming an optical planarization layer over the polysilicon layer; planarizing the optical planarization and polysilicon layers down to the memory stack; forming a dielectric blocking layer over the memory stack and substrate; forming a patterning stack over the dielectric blocking layer, the patterning stack covering a portion of the memory stack; and removing the dielectric blocking, optical planarization, and polysilicon layers on opposite sides of the patterning stack.

Cost-effective method to form a reliable memory device with selective silicidation and resulting device

Integrated circuits and methods of forming the same are provided herein. In an embodiment, an integrated circuit includes a semiconductor substrate that has an isolated well. A multilayer metallization stack overlies the semiconductor substrate. The multilayer metallization stack includes a metal layer, a functional via, and a dummy metal feature. The metal layer includes a first line in electrical communication with the isolated well through a contact. The functional via is in electrical communication with the first line and the contact. The dummy metal feature is in electrical communication with the functional via.

Integrated circuits including a dummy metal feature and methods of forming the same

Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.

Method for producing integrated circuit memory cells with less dedicated lithographic steps

Methods of fabricating a dome-shaped MTJ TE and the resulting devices are provided. Embodiments include forming a MRAM stack having a laterally separated MTJ structures and the MRAM and a logic stack each having a SiN layer; forming first trenches through the MRAM stack to a portion of the SiN layer above an MTJ structure; forming second trenches through the SiN layer fully landing on an upper portion of the MTJ structures and removing the SiN layer of the logic stack; forming a TaN layer over the MRAM and logic stack; removing portions of the TaN layer on opposite sides of the MTJ structures and therebetween; forming an oxide layer over the MRAM and logic stacks; and forming vias through the oxide layer of the MRAM stack down the TaN layer above MTJ structures and a via through the logic stack.

Top electrode dome formation

A semiconductor device with a temporary discharge path. During back-end-of-line (BEOL), the temporary discharge path discharges a plasma charge collected in a device well, such as a floating p-type well. After processing, the temporary discharge path is rendered non-function, enabling the device to function properly.

Plasma discharge path

Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates.

Method of forming split-gate cell for non-volative memory devices

A semiconductor device is disclosed. The semiconductor device includes a substrate comprises a plurality of metal layers. The semiconductor device also includes dielectric posts disposed in the metal layers. The density of the dielectric posts in the metal layers is equal to about 15-25%.

Dielectric posts in metal layers

Back-side MOM/MIM structures are integrated on a device with front-side circuitry. Embodiments include forming a substrate having a front side and a back side that is opposite the front side, the substrate including circuitry on the front side of the substrate; and forming a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or a combination thereof on the back side of the substrate. Other embodiments include forming a through-silicon via (TSV), in the substrate, connecting the MOM capacitor, the MIM capacitor, or a combination thereof to the circuitry on the front side of the substrate.

Back-side MOM/MIM devices

Semiconductor devices and methods for forming a semiconductor device are disclosed. The semiconductor device includes a die. The die includes a die substrate having first and second major surfaces. The semiconductor device includes a power module disposed below the second major surface of the die substrate. The power module is electrically coupled to the die through silicon via (TSV) contacts.

Device with integrated power supply

Growing community of inventors

Singapore, Singapore

Soh Yun Siah