Samsung Electronics Co., Ltd.

So-Young Lim

Pa-Lan Lee

Jeong-Kyu Ha

Na-rae Shin

Kyoung-Suk Yang

Donghan Kim

Jae-Min Jung

Kyong-Soon Cho

Kwan-Jai Lee

Jin-Woo Park

Jung-Hwan Kim

Yun-seok Choi

Sung-Woo Park

Kwang-Jin Bae

Hyun-A Kim

Hee Seok Lee

Sang-Heui Lee

In-won O

Sang-Heul Lee

Eun Seok Song

A test pad structure includes a plurality of test pads and a plurality of connection leads. The test pads are sequentially arranged from a wiring pattern on a substrate and in rows parallel with one another. The test pads include first and second groups of test pads, the first group having at least one pad and the second group having at least two pads. The connection leads extend from end portions of the wiring pattern to be connected to the test pads. The connection leads include at least one inner lead passing between the at least two pads of the second group and arranged in a first row closest to the first group. The at least one inner lead may be connected to at least one pad of the at least two pads of the second group arranged in a second row next to the first row.

Test pad structure, a pad structure for inspecting a semiconductor chip and a wiring substrate for a tape packaging having the same

A chip on film (COF) package includes a film substrate, first leads on a first surface of the film substrate, the first leads having a first length, and second leads on the first surface of the film substrate, the second leads having a second length larger than the first length, first via plugs penetrating the film substrate and connected to first ends of the first leads, and second via plugs penetrating the film substrate and connected to first ends of the second leads, and first connection leads on a second surface of the film substrate facing the first surface, the first connection leads having first ends connected to the first via plugs, and second connection leads on the second surface of the film substrate, the second connection leads having first ends electrically connected to the second via plugs.

Chip on film package including distributed via plugs

A chip on film package includes a flexible base film having a first surface and a second surface opposite to each other that includes at least one through hole therein, a plurality of wirings disposed on the first surface and the second surface of the base film, respectively, that include a first lead and a second lead connected to each other through the at least one through hole, and a display panel driving chip and a touch panel sensor chip, each mounted on any one of the first surface and the second surface of the base film, wherein at least one of the display panel driving panel and the touch panel sensor chip is electrically connected to the first and second leads.

Chip on film package and display device including the same

A COF substrate may include a base film, first upper conductive patterns, at least one second upper conductive pattern and lower conductive patterns. The first upper conductive patterns may be arranged on an upper surface of the base film. Each of the first upper conductive patterns may have an inner pattern and an outer pattern spaced apart from each other. The second upper conductive pattern may be arranged on the upper surface of the base film between the first upper conductive patterns. The lower conductive patterns may be arranged on a lower surface of the base film. The lower conductive patterns may be electrically connected between the inner pattern and the outer pattern. Thus, conductive materials causing a short between the panel patterns may not exist between the inner pattern and the outer pattern on the upper surface of the base film.

Chip on film (COF) substrate, COF package and display device including the same

A semiconductor device includes an interposer mounting a semiconductor chip. The interposer includes a silicon substrate having a recessed region formed on a first surface, a first through via penetrating a first region of the silicon substrate from the first surface to an opposing second surface, an insulator disposed in the recessed region, and a first wire pattern at least partially disposed on the insulator and electrically connecting the first through via to the semiconductor chip.

Semiconductor device with interposer and method manufacturing same

A tape package providing a plurality of input and output portions each having a minimum pitch. The tape package includes a tape wiring substrate including first and second wirings, and a semiconductor chip mounted on the tape wiring substrate, and including a first edge, a first pad disposed adjacent to the first edge, and a second pad disposed to be farther spaced apart from the first edge than the first pad, where the first wiring is connected to a portion of the first pad that is spaced from the first edge by a first distance, and where the second wiring is connected to a portion of the second pad that is spaced from the first edge by a second distance that is greater than the first distance.

Tape package

A semiconductor chip carrier having multiple conductive layers separated from each other by dielectric layers, a chip bonding position at an intermediate portion of a top surface of the semiconductor chip carrier, and a bonding region spaced apart from the chip bonding position. The bonding region includes a first bonding region closest to the chip bonding position, a second bonding region most distant from the chip bonding position, and a third bonding region positioned between the first bonding region and the second bonding region. The first bonding region, the second bonding region and the third bonding region are electrically insulated from each other and the first bonding region is configured to carry a first voltage, the second bonding region is configured to carry a second voltage and the third bonding region is configured to carry a third voltage that is less than the first voltage and less than the second voltage.

Semiconductor package including power ball matrix and power ring having improved power integrity

A semiconductor housing package may be provided. The semiconductor housing package may include a mold layer, a housing chip, a redistribution structure, and a housing node. The mold layer may surround and partially expose the housing chip. The redistribution structure may be electrically connected to the housing chip and may be disposed on the mold layer. The housing node may be in contact with the redistribution structures. The semiconductor housing package may be disposed on a semiconductor base package and may constitute a semiconductor package structure along with the semiconductor base package. The semiconductor package structure may be disposed on a processor-based system.

Semiconductor housing package, semiconductor package structure including the semiconductor housing package, and processor-based system including the semiconductor package structure

A test pad structure may include a plurality of test pads and a plurality of connection leads. A plurality of the test pads may be sequentially arranged from a wiring pattern on a substrate and arranged in rows parallel with one another. The plurality of the test pads may include a first group of test pads having at least one pad arranged in a first row and a second group of test pads having at least two pads. A plurality of the connection leads may extend from end portions of the wiring pattern to be connected to the plurality of test pads. A plurality of the connection leads may include at least one inner lead passing between the at least two pads of the second group of the test pads arranged in a second row closest to the first group of the test pads. The at least one inner lead may be connected to at least one pad of the at least two pads of the second group of the test pads arranged in a third row next to the second row.

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Hwaseong-si, South Korea

So-Young Lim