Synopsys, Inc.

Iroc Technologies

Slimane Boutobza

Michael Nicolaidis

Michaël Nicolaidis

Andrea Costa

Sorin Ioan Popa

Disclosed herein are computer-implemented method, system, and computer-program product (non-transitory computer-readable storage medium) embodiments for automatic test-pattern generation (ATPG) validation. An embodiment includes parsing an ATPG input, semantically analyzing the ATPG input, generating a first HDL model based on the semantic analysis, creating an HDL testbench based on the first HDL model, simulating an ATE test of a circuit structure, and outputting a validation result of the circuit structure, based on the simulating. In some embodiments, the parsing may include lexical and/or syntactic analysis. The HDL model may represent the circuit structure as functionally equivalent to the ATPG input, as determined based on the semantic analysis. In some embodiments, the ATPG input includes a cycle-based test pattern for a first block of the ATPG input, and the HDL testbench includes event-based test patterns that mimic given ATE behavior. The HDL model may be smaller in size than the ATPG input.

Automatic testbench generator for test-pattern validation

A programmable built in self test, BIST, system for testing a memory, comprises an instruction register formed in the same chip as the memory; a circuit for loading the register by successive instructions, each instruction comprising at least one address control field, a first number (m) of operation fields, a number-of-operations field specifying a second number t+1, with t+1&#x2266;m; a circuit controlled by the address control field to determine successive addresses; and a cycle controller for executing, for each successive address, the second number (t+1) of successive operations, each of which is determined by one of the t+1 first operation fields.

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Grenoble, France

Slimane Boutobza