Lucent Technologies Inc.

Agere Systems Inc.

Agere Systems Guardian Corp.

Sivanand Simanapalli

Mazhar M Alidina

Larry R Tate

Mohammad Shafiul Mobin

Mark Ernest Thierbach

Richard Adam Cesari

Geoffrey Francis Burns

Xiao-An Wang

A method of assigning unique instruction codes to instructions in an instruction set is disclosed. Such an encoded instruction set is also disclosed. Instructions are grouped according to the particular resources used, where all of the instructions in a group have one or more resource types in common. The position of the highest order active bit in the code is used to identify which resource group a particular instruction belongs to. Instructions in a resource group reserve the same number of bits to identify the specific resources to be used, and no more bits are reserved than required. The remaining unassigned bits are used to encode particular command codes. When such an encoded command is decoded, the resource group is identified by determining the highest order active bit in the instruction. This information is used to determine which bits in the instruction are command bits and which are resource-identifying bits. The specific resource information is extracted and used to select the designated resources to be used in executing the command. This encoding scheme eliminates wasted bits in instructions and thereby increases the number of instructions which can be implemented.

Method for optimally encoding a set of instruction codes for a digital processor having a plurality of instruction selectable resource types and an associated optimized set of instruction codes

A near-orthogonal dual-MAC instruction set is provided which implements virtually the entire functionality of the orthogonal instruction set of 272 commands using only 65 commands. The reduced instruction set is achieved by eliminating instructions based on symmetry with respect to the result of the commands and by imposing simple restrictions related to items such as the order of data presentation by the programmer. Specific selections of commands are also determined by the double word aligned memory architecture which is associated with the dual-MAC architecture. The reduced instruction set architecture preserves the functionality and inherent parallelism of the command set and requires fewer command bits to implement than the full orthogonal set.

Near-orthogonal dual-MAC instruction set architecture with minimal encoding bits

A method and apparatus for reducing instruction cycles in a digital signal processor wherein the processor includes a multiplier unit, an adder, a memory, and at least one pair of first and second accumulators. The accumulators include respective guard, high and low parts. The method and apparatus enable vectoring the respective first and second high parts from the accumulators to define a single vectored register responsive to a single instruction cycle and processing the data in the vectored register.

Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architecture

The invention includes a method of identifying an extremum value and an index in a group of values where each value has an associated index. A count register is initialized to an initial count. A value from the group as well as a predetermined value are provided simultaneously to an arithmetic logic unit and a multiplexer. The value from the group and the predetermined value are compared in the arithmetic logic unit. A selector is set to one of a first or second logic state. In the first logic state the selector selects a minimum; in the second logic state the selector selects a maximum. One of the value and the predetermined value are selected as an extremum based on a flag set by the comparison in the arithmetic logic unit and the selector. The predetermined value is replaced with the extremum and the count register count is stored when the selector is set to a first state and the value is less than the predetermined value. The predetermined value is replaced with the extremum and the count register count is stored when the selector is set to the second state and the value is greater than the predetermined value.

Single-cycle accelerator for extremun state search

A convolutional encoder and method convolutionally encode input bits from an input frame. The convolutional encoder has a predetermined bit input source and a logic circuit. The predetermined bit input source inserts a plurality of predetermined bits into an input register with the input bits. The logic circuit has a plurality of shift registers, a plurality of polynomial generators, and an output generator. The plurality of shift registers shift the input register, including the predetermined bits, to generate shifted data. The plurality of polynomial generators generate respective polynomial values in a plurality of polynomial registers from the shifted data. The output generator generates output data in an output register from the polynomial values corresponding to convolutional encoding of the data in the input register.

Bit insertion approach to convolutional encoding

A device for shifting data in a cascade multiplexer shifter allows the shifter to be used in a full-length mode or in a split mode where the shifter is divided into two equal halves with upper and lower half fields thereof respectively receiving individual data numbers. Each data number is thereafter simultaneously shifted right or shifted left a given shift amount to effect a dual right or dual left shift function.

Shifter capable of split operation

In accordance with the invention, a method of generating a soft symbol confidence level for use in decoding a received digital signal includes calculating a difference between two potential next state accumulated costs to provide a soft symbol confidence level. Simultaneously with calculating the difference between two potential next state accumulated costs, performing a compare-select operation to identify one of the two potential next state accumulated costs as an extremum of the two present state accumulated costs.

Single-cycle, soft decision, compare-select operation using dual-add

There is disclosed, a method and apparatus for processing a signal in a pipeline. The method includes retrieving a present state cost. Simultaneously with receiving the present state cost, an estimated symbol and a received symbol are obtained, a difference between the received and estimated symbols is found, the difference between the received and esitmated symbols is squared, and the present state cost is added to the squared difference to generate a next state cost. The apparatus includes hardware to carry out the method.

Metric acceleration on dual MAC processor

A method of extracting an information bearing signal .omega.(n) from a base-band signal in the form of an inverse function with a digital signal processor. The processor includes memory and utilizes a minimum number of instructions stored in the memory. The base-band waveform comprises a plurality of complex-valued samples having respective I and Q components. The method includes the steps of receiving a first sample at an instant n having respective I(n) and Q(n) components and defining an interval for evaluating potential values for the I(n) and Q(n) components. Next, a step of transforming said I(n) and Q(n) components is performed to have respective threshold values residing in the predefined interval. Then, a step of estimating the transformed components with a series of non-inverted polynomial functions is carried out over the predefined interval. The method proceeds by extracting the information-bearing signal with the digital signal processor according to the instructions to evaluate the series of non-inverted polynomial functions.

FM discriminator with automatic gain control for digital signal

A data processor determines an overall extremum value of an input set of array data, with the input set of array data partitionable into a first set of array data and a second set of array data. The data processor includes a pair of compare-select circuits implemented in an adder as well as in an arithmetic-logic unit (ALU), respectively, which operate in parallel for respectively processing the first set and the second set, and for respectively determining first and second extremum values of the first set and the second set, respectively. A first compare-select circuit of the pair of compare-select circuits determines the overall extremum value of the input set of array data from the first and second extremum values. The first compare-select circuit also determines the location of the overall extremum value in the input set of array data. The computational complexity in determining extrema is reduced by implementing compare-select features in an adder in addition to an ALU to operate in parallel to reduce the number of processing cycles.

Determining an extremum value and its index in an array using a

A dual-MAC processor optimized so that two Viterbi ACS operations, including traceback bit storage, can be executed in two machine cycles is disclosed. The processor comprises a pair of adder arithmetic logic units connected to a common accumulator register bank and supporting full and split-mode add, subtract, and compare operations. Viterbi compare operations are executed using the subtract function and the sign bit is combined with a compare mode bit to generate a traceback output which indicates the proper traceback bit to store. When a compare operation is performed and a Viterbi mode bit is active, each generated traceback output is shifted into a traceback register for later use in a Viterbi traceback routine.

Mac processor with efficient Viterbi ACS operation and automatic

A method of efficient branch metric computation for a Viterbi convolutional decoder wherein a reduced and optimized set of branch metrics is distributed among one or more base sets is provided. A sequence of data transformations and associations are defined according to the connections of the delay elements in the convolutional encoder to its outputs. Each encoder state is associated with one of the base sets and one of several groups of path metric equations. During the add portion of the add-compare-select phase of Viterbi decoding, a branch metric value is extracted from the base set associated with the encoder state being evaluated. The group of path metric equations associated with state being evaluated are evaluated using the extracted branch metric value. The results of the addition are then be processed according to the remaining steps of the Viterbi algorithm.

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Allentown, PA, United States of America

Sivanand Simanapalli