Texas Instruments Corporation

Siva Prakash Gurrum

Manu Joseph Prakuzhy

Vikas I Gupta

Amit Sureshkumar Nangia

Gregory Eric Howard

Darvin R Edwards

Rajiv Carl Dunne

Donald Charles Abbott

Bernardo Gallegos

Sreenivasan Kalyani Koduri

Christopher Daniel Manack

Masood Murtuza

Ken Pham

Matthew David Romig

Michael A Lamson

Stefan Wlodzimierz Wiktor

Saumya Gandhi

Paul Joseph Hundt

Janakiraman Seetharaman

Kapil Heramb Sahasrabudhe

Kazunori Hayata

Hung-Yun Lin

Daryl R Heussner

Young-Joon Park

Manu A Prakuzhy

Blake Barrett Travis

An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive connector and a die that has an active side and a non-active side. The active side of the die is connected to the electrically conductive connector via interconnects. A molding compound encapsulates the die and portions of the electrically conductive connector. A thermally conductive contact extends from a thermal hotspot on the die to an entry surface of the molding compound.

Integrated circuit package having enhanced thermal dissipation structure

An integrated circuit (IC) includes semiconductor substrate with a metal stack including a lower, upper and a top metal layer that includes bond pads and a detection bond pad (DBP). A wirebond damage detector (WDD) includes the DBP over a first and second connected structure. The first and second connected structures both include spaced apart top segments of the upper metal layer coupled to spaced apart bottom segments of the lower metal layer. The DBP is coupled to one end of the first connected structure, and ≥1 metal trace is coupled to another end extending beyond the DBP to a first test pad. The second connected structure includes metal traces coupled to respective ends each extending beyond the DBP to a second test pad and to a third test pad.

Wire bond damage detector including a detection bond pad over a first and a second connected structures

An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.

IC having a metal ring thereon for stress reduction

In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.

Packaged multichip module with conductive connectors

An integrated circuit (IC) includes semiconductor substrate with a metal stack including a lower, upper and a top metal layer that includes bond pads and a detection bond pad (DBP). A wirebond damage detector (WDD) includes the DBP over a first and second connected structure. The first and second connected structures both include spaced apart top segments of the upper metal layer coupled to spaced apart bottom segments of the lower metal layer. The DBP is coupled to one end of the first connected structure, and &#x2265;1 metal trace is coupled to another end extending beyond the DBP to a first test pad. The second connected structure includes metal traces coupled to respective ends each extending beyond the DBP to a second test pad and to a third test pad.

A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has leads of a first subset that alternate with leads of a second subset. The leads of the first and second subsets have elongated straight lead portions that are parallel to each other in a planar array. A cover layer of insulating material is located over portions of un-encapsulated lead surfaces. The portions of the leads of the first and second subsets that don't have the cover layer have a metallurgical configuration that creates an affinity for solder wetting.

Spot-solderable leads for semiconductor device packages

A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.

Semiconductor package with filler particles in a mold compound

A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.

Semiconductor package with a wire bond mesh

A method of semiconductor device packaging to form a packaged semiconductor device includes providing (i) a vertical power semiconductor device die including a semiconductor substrate including a control node, a source or emitter on a top side or on a bottom side of the substrate, and a drain or a collector on another of the top side the bottom side, a backside metal (BSM) layer on the bottom side, and (ii) a leadframe. The leadframe includes a patterned die pad that includes a common continuous base portion and a two-dimensional array of spaced apart posts extending up from the base portion, with a separate solder cap on a top of the posts. The BSM layer is placed on the solder caps, and reflow processing bonds the BSM layer to the solder caps.

Patterned die pad for packaged vertical semiconductor devices

A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.

Growing community of inventors

Allen, TX, United States of America

Siva Prakash Gurrum