Yangtze Memory Technologies Co., Ltd.

Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.

Siping Hu

Wei Liu

Shiqi Huang

Bater Chelon

Shu Wu

Yongqing Wang

Jifeng Zhu

Lei Xue

Lan Yao

Ziqun Hua

He Chen

Lina Miao

Pengan Yin

Yucheng Zhang

Yi Zhao

Zhen Pan

Jinwen Dong

Sheng'an Xiao

The present disclosure discloses a three-dimensional (3D) memory, which includes a peripheral wafer and an array wafer. The peripheral wafer includes a first peripheral structure and a second peripheral structure. The array wafer includes a substrate, a structure to be tested and multiple interconnecting portions. The substrate includes a first well region and a second well region. The array wafer includes the structure to be tested which has a first connecting portion, a second connecting portion, and multiple interconnecting portions. The first peripheral structure is connected to the first well region and the first connecting portion of the structure to be tested by the first interconnecting portion and the second interconnecting portion respectively. The second peripheral structure is connected to the second well region and the second connecting portion of the structure to be tested by the third interconnecting portion and the fourth interconnecting portion respectively.

3D memory device

Disclosed are three-dimensional (3D) memory devices and fabricating methods thereof. In some embodiments, a disclosed memory device comprises a wafer structure having a sealing region and a chip region. The wafer structure comprises a substrate, a memory string array on a first side of the substrate in the chip region, a first protection structure and a second protection structure on the first side of the substrate in the sealing region, and a first contact and a second contact extending through the substrate in the sealing region. The first contact is in contact with the first protection structure, and the second contact is in contact with the second protection structure.

Three-dimensional memory devices and fabricating methods thereof

Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method for a 3D NAND memory device includes providing a substrate, forming at least one contact pad over a first portion of a face side of the substrate, forming memory cells over a second portion of the face side of the substrate, depositing a first dielectric layer to cover the at least one contact pad and the memory cells of, forming a first connecting pads over the first dielectric layer and connected to the at least one contact pad and the memory cells, bonding the first connecting pads with second connecting pads of a peripheral structure, and exposing the at least one contact pad from a back side of the substrate.

Contact pads of three-dimensional memory device and fabrication method thereof

Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes providing a substrate, forming memory cells over the substrate, depositing a first dielectric layer to cover the memory cells, forming at least one contact pad over the substrate, depositing a second dielectric layer over the at least one contact pad, forming first connecting pads over the second dielectric layer, bonding the first connecting pads with second connecting pads of a peripheral structure, and exposing the at least one contact pad from a back side of the substrate.

Three-dimensional memory device comprising contact pads exposed by an opening passing through layer stack and fabrication method thereof

Embodiments of bonded 3D memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a plurality of first NAND memory strings and a plurality of first BLs. At least one of the first BLs may be conductively connected to a respective one of the first NAND memory strings. The first semiconductor structure also includes a plurality of first conductor layers, and a first bonding layer having a plurality of first bit line bonding contacts conductively connected to the plurality of first BLs and a plurality of first word line bonding contacts conductively connected to the first conductor layers. A second semiconductor structure includes a plurality of second NAND memory strings and a plurality of second BLs.

Method for forming a three-dimensional (3D) memory device having bonded semiconductor structures

A metal-dielectric bonding method includes providing a first semiconductor structure including a first semiconductor layer, a first dielectric layer on the first semiconductor layer, and a first metal layer on the first dielectric layer, where the first metal layer has a metal bonding surface facing away from the first semiconductor layer; planarizing the metal bonding surface; applying a plasma treatment on the metal bonding surface; providing a second semiconductor structure including a second semiconductor layer, and a second dielectric layer on the second semiconductor layer, where the second dielectric layer has a dielectric bonding surface facing away from the second semiconductor layer; planarizing the dielectric bonding surface; applying a plasma treatment on the dielectric bonding surface; and bonding the first semiconductor structure with the second semiconductor structure by bonding the metal bonding surface with the dielectric bonding surface.

Metal-dielectric bonding method and structure

In certain aspects, a method for controlling wafer stress is disclosed. A semiconductor film is formed on a backside of a wafer. The wafer is deformed by stress associated with a front-side semiconductor structure on a front side of the wafer opposite to the backside of the wafer. A laser application region of the semiconductor film is determined. A laser anneal process is performed in the laser application region of the semiconductor film.

Wafer stress control using backside film deposition and laser anneal

A metal-dielectric bonding method includes providing a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes: a first semiconductor layer including a complementary metal-oxide-semiconductor device, a first dielectric layer on the first semiconductor layer, and a first metal layer on the first dielectric layer, the first metal layer having a metal bonding surface. The metal bonding surface is planarized and a plasma treatment is applied thereto. The second semiconductor structure includes a second semiconductor layer including a pixel wafer, and a second dielectric layer on the second semiconductor layer, the second dielectric layer having a dielectric bonding surface. The dielectric bonding surface is planarized and a plasma treatment is applied thereto. The first and second semiconductor structures are bonded together by bonding the metal bonding surface with the dielectric bonding surface.

Bonded three-dimensional memory devices having bonding layers

Embodiments of bonded 3D memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a first semiconductor structure, which includes a plurality of first NAND memory strings, a plurality of first BLs, at least one of the first BLs being conductively connected to a respective one of the first NAND memory strings; and a first bonding layer having a plurality of first bit line bonding contacts conductively connected to the plurality of first BLs, respectively. The 3D memory device further includes a second semiconductor structure, which includes a plurality of second NAND memory strings, a plurality of second BLs, at least one of the second BLs being conductively connected to a respective one of the second NAND memory strings, and a second bonding layer having a plurality of second bit line bonding contacts conductively connected to the plurality of second BLs, respectively.

Bonded three-dimensional memory devices and methods for forming the same

Embodiments of bonded 3D memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first memory stack having a plurality of first conductor layers and a first bonding layer having a plurality of first word line bonding contacts conductively connected to the plurality of first conductor layers, respectively. A second semiconductor structure includes a second memory stack having a plurality of second conductor layers and a second bonding layer having a plurality of second word line bonding contacts conductively connected to the plurality of second conductor layers, respectively. The 3D memory device also includes a bonding interface between the first bonding layer and the second bonding layer, at which the first word line bonding contacts are in contact with the second word line bonding contacts.

The invention relates to the field of semiconductor, more particularly, to a preparation process of image sensors, comprising: Step S, providing a semiconductor structure, a top of which is provided with a groove, and leads being formed in said groove, the top of said semiconductor structure and an exposed surface of said groove are covered with a first dielectric layer; Step S: depositing a second dielectric layer covering the upper surface of said first dielectric layer and said leads and filling said groove; Step S: performing a reversed-etching process to thin said second dielectric layer, and to form a convex structure on a surface of said second dielectric layer above the groove; Step S: performing a planarization process to said second dielectric layer to improve surface evenness of said second dielectric layer after grinding by the convex structure.

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Wuhan, China

Siping Hu