Globalfoundries Inc.

Globalfoundries U.S. Inc.

Applied Materials, Inc.

Sipeng Gu

Haiting Wang

Jiehui Shu

Yanping Shen

Akshey Sehgal

Xinyuan Dou

Judson Robert Holt

Qintao Zhang

Xiang Hu

Halting Wang

Xusheng Kevin Wu

Wei Zou

Huang Liu

Zhiguo Sun

Alok Vaid

Lokesh Subramany

Jeffrey Chee

Yi Qi

Sunil Kumar Singh

Scott Beasor

Jianwei Peng

Ravi Prakash Srivastava

Baofu Zhu

Kyu-Ha Shim

Sandeep Gaan

Yanzhen Wang

Hsien-Ching Lo

Yuping Ren

Baonian Guo

Kyuha Shim

Guoliang Zhu

Duohui Bei

Wenhe Lin

Hong Yu

John J Hautala

Shesh Mani Pandey

Zhenyu Hu

Yi Zheng

Keith Howard Tabakman

Hongliang Shen

Abner Bello

Lixia Lei

Wen-Pin Peng

Jun Lian

Yue Hu

Xiaoming Yang

Danni Chen

Gregory Costrini

Adam Selsley

Xiaobo Chen

Rinus Lee

Bangun Indajang

Disclosed herein are approaches for forming contacts in a 4Fvertical dynamic random-access memory device. One method includes forming a hardmask over a plurality of pillars and over a plurality of anchors, wherein the pillars are separated from one another by a STI, and removing the STI and etching through the hardmask to form a plurality of gate trenches. The method may further include delivering a capping material to the pillars at a non-zero angle relative to a perpendicular extending from an upper surface of the pillars, wherein the capping material forms a capping layer along an upper portion of the pillars without forming the capping layer along a lower portion of the pillars. The method may further include etching the pillars to trim the lower portion of the pillars, and forming a plurality of contacts in the upper portion of the pillars.

Vertical FinFet formation using directional deposition

Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

Ion implantation to reduce nanosheet gate length variation

The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.

Gate structures

Structures for a semiconductor device that include dielectric isolation and methods of forming a structure for a semiconductor device that includes dielectric isolation. A semiconductor body includes a cavity, first and second gate structures extending over the semiconductor body, and a semiconductor layer including first and second sections on the semiconductor body. The first section of the semiconductor layer is laterally positioned between the cavity and the first gate structure, and the second section on the semiconductor layer is laterally positioned between the cavity and the second gate structure. An isolation structure is laterally positioned between the first and second sections of the semiconductor layer. The isolation structure includes a dielectric layer and a sidewall spacer having first and second sections. The dielectric layer includes a first portion in the cavity and a second portion between the first and second sections of the sidewall spacer.

Semiconductor devices having late-formed isolation structures

An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.

Memory device comprising a top via electrode and methods of making such a memory device

One illustrative device disclosed herein includes a memory cell positioned in a first opening in at least one layer of insulating material. The memory cell comprises a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer defines a spacer opening. The device also comprises a top electrode positioned within the spacer opening.

Top electrode for a memory device and methods of making such a memory device

A P-type field effect transistor (PFET) device and a method for fabricating a PFET device using fully depleted silicon on insulator (FDSOI) technology is disclosed. The method includes introducing germanium into the channel layer using ion implantation. This germanium implant increases the axial stress in the channel layer, improving device performance. This implant may be performed at low temperatures to minimize damage to the crystalline structure. Further, rather than using a long duration, high temperature anneal process, the germanium implanted in the channel layer may be annealed using a laser anneal or a rapid temperature anneal. The implanted regions are re-crystallized using the channel layer that is beneath the gate as the seed layer. In some embodiments, an additional oxide spacer is used to further separate the raised source and drain regions from the gate.

Localized stressor formation by ion implantation

A method may include providing a device structure in the semiconductor device. The device structure may include a buried device contact, a first dielectric layer, disposed over the buried device contact; and a device element, where the device element includes a TiN layer. The method may include implanting an ion species into the TiN layer, wherein the ion species comprises a seed material for selective tungsten deposition.

Techniques for selective tungsten contact formation on semiconductor device elements

The present disclosure relates to semiconductor structures and, more particularly, to self-aligned contacts and methods of manufacture. The structure includes: adjacent diffusion regions located within a substrate material; sidewall structures above an upper surface of the substrate material, aligned on sides of the adjacent diffusion regions; and a contact between the sidewall structures and extending to within the substrate material between and in electrical contact with the adjacent diffusion regions.

Self-aligned contact

A method of isolating sections of the channel layer in a SOI workpiece is disclosed. Rather than etching material to create trenches, which are then filled with a dielectric material, ions are implanted into portions of the channel layer to transform these implanted regions from silicon or silicon germanium into an electrically insulating material. These ions may comprise at least one isolating species, such as oxygen, nitrogen, carbon or boron. This eliminates various processes from the fabrication sequence, including an etching process and a deposition process. Advantageously, this approach also results in greater axial strain in the channel layer, since the channel layer is continuous across the workpiece.

Isolation method to enable continuous channel layer

A method of forming a metal oxide semiconductor field effect transistor with improved gate-induced drain leakage performance, the method including providing a semiconductor substrate having a gate trench formed therein, performing an ion implantation process on upper portions of sidewalls of the gate trench to make the upper portions more susceptible to oxidation relative to non-implanted lower portions of the sidewalls, and performing an oxidation process on surfaces of the substrate, wherein the implanted upper portions of the sidewalls develop a thicker layer of oxidation relative to the non-implanted lower portions of the sidewalls.

Technique for reducing gate induced drain leakage in DRAM cells

A method of modifying a high-resistivity substrate so that the substrate may be electrostatically clamped to a chuck is disclosed. The bottom surface is implanted with a resistivity-reducing species. In this way, resistivity of the bottom surface of the substrate may be greatly reduced. In some embodiments, to implant the bottom surface, a coating is applied to the top surface. After application of the coating, the substrate is flipped so that the front surface contacts the top surface of the chuck. The ions are then implanted into the exposed bottom surface to create the low resistivity layer. The resistivity of the low resistivity layer proximate the bottom surface after implant may be less than 1000 ohm-cm. Once the bottom surface has been implanted, the substrate may be processed conventionally. The low resistivity layer may later be removed by wafer backside thinning processes.

Handling for high resistivity substrates

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

Transistors with separately-formed source and drain

Structures for a single diffusion break and methods of forming a structure for a single diffusion break. A cut is formed in a semiconductor fin. A single diffusion break includes a first dielectric layer in the cut and a second dielectric layer over the first dielectric layer. The first dielectric layer is comprised of a first material, and the second dielectric layer is comprised of a second material having a different composition than the first material. The second dielectric layer includes a first portion over the first dielectric layer and a second portion over the first portion. The first portion of the second dielectric layer has a first horizontal dimension, and the second portion of the second dielectric layer has a second horizontal dimension that is greater than the first horizontal dimension.

Single diffusion breaks including stacked dielectric layers

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Clifton Park, NY, United States of America

Sipeng Gu