Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Other

Sin Sim Tan

Sivakumar Radhakrishnan

Mark A Schmisseur

Lily Pao Looi

Kenneth C Haren

Pankaj Kumar

Stephan Jourdan

Srikanth T Srinivasan

Michael T Klinglesmith

Bradley A Burres

Eric Dahlen

Thomas M Slaight

Brian M Leitner

Geetani R Edirisooriya

Marc Tim Jones

David C Lee

Matthew R Wilcox

Saptarshi Mondal

Vinodh Gopal

Wajdi K Feghali

Akhilesh Kumar

Stanley Steve Kulick

Suresh S Chittor

Bruce A Tennant

Manoj Khare

Chih-Cheh Chen

Jonathan Nick Spitz

Thomas C Brown

Rajesh S Pamujula

Altug Koker

James A Sutton, Ii

Anant S Deval

Suneeta Sah

Selim Bilgin

Dmitry Petrov

Yi-Feng Liu

John A Urbanski

Rajee S Ram

Siva Balasubramanian

Rami A Naqib

Jasper Balraj

Christopher Van Beek

S Steven Kulick

Stephan J Jourdan

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

Presentation of direct accessed storage under a logical drive model

Methods and apparatus related to enhanced Cyclical Redundancy Check (CRC) circuit based on Galois-Field arithmetic are described. In one embodiment, a plurality of exclusive OR logic include first exclusive OR logic and second exclusive OR logic. First Galois Field multiplier logic multiplies a first output from the first exclusive OR logic and a first portion of a plurality of portions of the input data. Second Galois Field multiplier logic multiplies a second output from the second exclusive OR logic and a second portion of the plurality of portions of the input data. Other embodiments are also disclosed and claimed.

Enhanced cyclical redundancy check circuit based on galois-field arithmetic

Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic

Methods and apparatus for integration of a processor and an input/output hub are described. In one embodiment, a sideband signal may cause change in a power management state of a processor or an integrated I/O logic. A single integrated circuit die may include both the processor and the integrated I/O logic. Other embodiments are also disclosed.

Integration of processor and input/output hub

Methods and apparatus relating squelch filtration to limit false wakeups are described. In one embodiment, a squelch logic generates a wakeup event for an agent based on occurrence of a number of pulses (originating from another agent) during a time period. Other embodiments are also disclosed.

Limiting false wakeups of computing device components coupled via links

Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.

Dynamic and idle power reduction sequence using recombinant clock and power gating

In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed.

Dynamic squelch detection power control

A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts.

Power measurement techniques of a system-on-chip (SOC)

Detecting and flushing maximal length packets is set forth herein. In one embodiment, the method comprises receiving a flushing event and, in response to the flushing event, repeatedly detecting a maximum length packet of write data from a write combining storage area and flushing the detected maximum length packet to a target input/output (I/O) device over a bus. Each maximal length packet is a packet of maximum payload of write data that can be formulated within in the write combining storage area while adhering to packet protocol rules for the bus.

Maximal length packets

A forwarding device compares a first address from a first coherent input/output (I/O) transaction with an address from at least one processor-issued transaction to determine if an address conflict exists. The forwarding device completes a first processor-issued transaction of the at least one processor-issued transaction if the address conflict exists and rejects the first coherent I/O transaction. The forwarding device holds remaining processor transactions of the at least one processor-issued transaction that have an address conflict with the first address of the first coherent I/O transaction. The forwarding device transmits the first coherent I/O transaction to an external I/O device, waits for the first coherent I/O transaction to return from the external I/O device, and completes the first coherent I/O transaction. The forwarding device releases the remaining processor transactions once the first coherent I/O transaction has been completed.

Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactions

Various methods and apparatuses to deactivating the mechanism to resolve instruction starvation if an agent which issued a first transaction does not reissue the first transaction within a predefined time period.

Method and apparatus to resolve instruction starvation

Growing community of inventors

Portland, OR, United States of America

Sin Sim Tan