Stmicroelectronics S.r.l.

Stmicroelectronics(tours) Sas

Simone Rascuna′

Mario Giuseppe Saggio

Gabriele Bellocchi

Alfio Guarnera

Anna Bassi

Paolo Badala′

Jean-Michel Simonnet

Fabrizio Roccaforte

Sophie Ngo

Giuseppe Greco

Francesco Lizio

Claudio Chibbaro

Filippo Giannazzo

Marco Santoro

Merged-PiN-Schottky, MPS, device comprising: a solid body having a first electrical conductivity; an implanted region extending into the solid body facing a front side of the solid body, having a second electrical conductivity opposite to the first electrical conductivity; and a semiconductor layer extending on the front side, of a material which is a transition metal dichalcogenide, TMD. A first region of the semiconductor layer has the second electrical conductivity and extends in electrical contact with the implanted region, and a second region of the semiconductor layer has the first electrical conductivity and extends adjacent to the first region and in electrical contact with a respective surface portion of the front side having the first electrical conductivity.

Contextual formation of a junction barrier diode and a Schottky diode in a MPS device based on silicon carbide, and MPS device

Process for manufacturing a 3C—SiC layer, comprising the steps of: providing a wafer of 4H—SiC, provided with a surface; heating, through a LASER beam, a selective portion of the wafer at least up to a melting temperature of the material of the selective portion; allowing the cooling and crystallization of the melted selective portion, thus forming the 3C—SiC layer, a Silicon layer on the 3C—SiC layer and a carbon-rich layer above the Silicon layer; completely removing the carbon-rich layer and the Silicon layer, exposing the 3C—SiC layer. If the Silicon layer is maintained on the 4H—SiC wafer, the process leads to the formation of a Silicon layer on the 4H—SiC wafer. The 3C—SiC or Silicon layer thus formed may be used for the integration, even only partial, of electrical or electronic components.

Process for working a wafer of 4H—SiC material to form a 3C—SiC layer in direct contact with the 4H—SiC material

Overvoltage protection circuits are provided. In some embodiments, an overvoltage protection circuit includes a first diode made of a first semiconductor material having a bandgap width greater than that of silicon. A second diode is included and is electrically cross-coupled with the first diode. The second diode is made of a second semiconductor material different from the first semiconductor material.

Overvoltage protection device

A Junction Barrier Schottky device includes a semiconductor body of SiC having a first conductivity. An implanted region having a second conductivity, extends into the semiconductor body from a top surface of the semiconductor body to form a junction barrier diode with the semiconductor body. An electrical terminal is in ohmic contact with the implanted region and in direct electrical contact with the top surface, laterally to the implanted region, to form a Schottky diode with the semiconductor body. The implanted region is formed by a first and a second portion electrically connected directly to each other and aligned along an alignment axis transverse to the top surface. Orthogonally to the alignment axis, the first portion has a first maximum width and the second portion has a second maximum width greater than the first maximum width.

JBS device with improved electrical performances, and manufacturing process of the JBS device

A merged-PN-Schottky, MPS, diode includes an N substrate, an N-drift layer, a P-doped region in the drift layer, an ohmic contact on the P-doped region, a plurality of cells within the P-doped region and being portions of the drift layer where the P-doped region is absent, an anode metallization on the ohmic contact and on said cells, to form junction-barrier contacts and Schottky contacts respectively. The P-doped region has a grid-shaped layout separating from one another each cell and defining, together with the cells, an active area of the MPS diode. Each cell has a same geometry among quadrangular, quadrangular with rounded corners and circular; and the ohmic contact extends at the doped region with continuity along the grid-shaped layout.

Semiconductor MPS diode with reduced current-crowding effect and manufacturing method thereof

A method for manufacturing a SiC-based electronic device, that includes implanting, at a front side of a solid body of SiC having a conductivity of N type, dopant species of P type, thus forming an implanted region that extends in depth in the solid body starting from the front side and has a top surface co-planar with said front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region at temperatures comprised between 1500° C. and 2600° C. so as to form an ohmic contact region including one or more carbon-rich layers, for example graphene and/or graphite layers, in the implanted region and, simultaneously, activation of the dopant species of P type.

Doping activation and ohmic contact formation in a SiC electronic device, and SiC electronic device

A manufacturing method of an anchorage element of a passivation layer, comprising: forming, in a semiconductor body made of SiC and at a distance from a top surface of the semiconductor body, a first implanted region having, along a first axis, a first maximum dimension; forming, in the semiconductor body, a second implanted region, which is superimposed to the first implanted region and has, along the first axis, a second maximum dimension smaller than the first maximum dimension; carrying out a process of thermal oxidation of the first implanted region and second implanted region to form an oxidized region; removing said oxidized region to form a cavity; and forming, on the top surface, the passivation layer protruding into the cavity to form said anchorage element fixing the passivation layer to the semiconductor body.

Manufacturing method of an element of an electronic device having improved reliability, and related element, electronic device and electronic apparatus

An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

Silicon carbide power device with improved robustness and corresponding manufacturing process

A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.

Wide bandgap semiconductor switching device with wide area Schottky junction, and manufacturing process thereof

Wide bandgap semiconductor switching device with wide area schottky junction, and manufacturing process thereof

An embodiment of a semiconductor structure for a power device integrated on a semiconductor substrate, of a first type of conductivity, and comprising:&#x2014;an epitaxial layer, of said first type of conductivity, made on said semiconductor substrate, and having a plurality of column structures, of a second type of conductivity, to define a charge balancing region;&#x2014;an active surface layer made on said epitaxial layer for housing a plurality of active regions; said epitaxial layer comprising a semiconductor separating layer arranged between the charge balancing region and the active surface layer, said semiconductor separating layer decoupling said column structures from said active regions.

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Catania, Italy

Simone Rascuna′