Chartered Semiconductor Manufacturing Ltd (corporation)

Other

Chartered Semiconductor

Simon Yew-Meng Chooi

Mei Sheng Zhou

Subhash Gupta

Yi Liang Xu

Mei-Sheng Zhou

John Leonard Sudijono

Sudipto Ranendra Roy

Yakub Aliyu

Paul Kwok Keung Ho

Paul Kwok Ho

Kin Leong Pey

Wenhe Lin

Xu Yi

Sangki Hong

Lap Chan

Siu Choon Ng

Kwok Keung Paul Ho

Joseph Zhifeng Xie

Licheng Han

Christopher Lim

Hardy Chan

Alex See

Jia Zhen Zheng

Yelehanka Ramachandramurthy Pradeep

Jian Xun Li

Henry Gerung

Luona Goh

Zhong Dong

Zainab Ismail

Siew Lok Toh

Jianxun Li

Vincent Sih

Ping Yu Ee

Liang Choo Hsia

Sang Yee Loong

Soh Yun Siah

Eng Hua Lim

Chew Hoe Ang

Liu Huang

Meisheng Zhou

Randall Cha

Raymond Joy

Vijai Kumar Chhagan

Wee Leng Tan

Victor Seng-Keong Lim

Wen Jun Liu

Jian-Hui Ye

Yin-Min Felicia Goh

Siew Yong Kong

Tak Yan Tse

Chian Yuh Sin

Vijai Komar Chhagan

Young-Tong Tsai

Jian-Xun Li

Jai Zhen Zheng

Tong Earn Tay

Subbash Gupta

Jianhui Ye

Gautam Sarkar

Loh-Nah Luona Goh

Siew-Lok Toh

Tong-Earn Tay

Sang Ki Hong

Teck Wee Lim

Cher Sian Chua

A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding

Methods of preparing conductive regions such as source/drain regions for silicidation procedures, has been developed. The methods feature removal of native oxide as well as removal of deposited arsenic based defects from conductive surfaces prior to deposition of a metal component of subsequently formed metal silicide regions. Arsenic ions implanted for N type source/drain regions are also implanted into insulator regions such as insulator filled shallow trench isolation regions. A hydrofluoric acid cycle used as a component of the pre-silicidation preparation procedure can release arsenic from the shallow trench isolation regions in the form of arsenic based defects, which in turn can re-deposit on the surface of source/drain region. Therefore pre-silicidation preparation treatments described in this invention feature removal of both native oxide and arsenic based defects from conductive surfaces prior to metal silicide formation. Methods include wet etch procedures featuring hydrofluoric acid and hydrogen peroxide, as well as spin dry and dry etch procedures both employed post hydrofluoric acid treatment to remove re-deposited arsenic based defects.

Methods for elimination of arsenic based defects in semiconductor devices with isolation regions

A method of fabricating at least one damascene opening comprising the following steps. A structure having at least one exposed conductive structure is provided. A dielectric barrier layer over the structure and the at least one exposed conductive structure. A lower low-k dielectric layer is formed over the dielectric barrier layer. An upper low-k dielectric layer is formed over the lower low-k dielectric layer. An SRO etch stop layer is formed between the lower low-k dielectric layer and the upper low-k dielectric layer and/or an SRO hard mask layer is formed over the upper low-k dielectric layer. At least the upper and lower low-k dielectric layers are patterned to form the at least one damascene opening exposing at least a portion of the at least one conductive structure, wherein the at least one SRO layer has a high etch selectivity relative to the lower and upper low-k dielectric layers.

Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics

The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Arand divalent Arare selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to: 

Poly(arylene ether) dielectrics

Method of improving adhesion of low dielectric constant films to other dielectric films and barrier metals in a damascene process are achieved. In one method, a low dielectric constant material layer is deposited on a substrate. Silicon ions are implanted into the low dielectric constant material layer. Thereafter, a TEOS-based silicon oxide layer is deposited overlying the low dielectric constant material whereby there is good adhesion between low dielectric constant material layer and the TEOS-based silicon oxide layer. In another method, a low dielectric constant material layer is deposited on a substrate. A silicon-based dielectric layer is deposited overlying the low dielectric constant material wherein the silicon-based dielectric layer is not silicon oxide whereby there is good adhesion between the low dielectric constant material layer and the silicon-based dielectric layer.

Method to improve adhesion of dielectric films in damascene interconnects

Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are silicon implanted and silicided. The PMOS gate has the higher work function.

Dual metal gate process: metals and their silicides

Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.

Copper diffusion deterrent interface

Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are oxygen implanted and oxidized. The PMOS gate has the higher work function.

Methods to form dual metal gates by incorporating metals and their conductive oxides

The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure:wherein n=5 to 10000 and monovalent Arand divalent Arare selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:

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Singapore, Singapore

Simon Yew-Meng Chooi