Adeia Semiconductor Bonding Technologies Inc.

Simon McElrea

Belgacem Haba

Wael Zohni

Suzette Keefe Pangrle

Scott P McGrath

Jeffrey S Leal

Loreto Cantillep

Ravi Shenoy

Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.

Stacked die assembly having reduced stress electrical interconnects

A microelectronic package includes a subassembly, a second substrate, and a monolithic encapsulant. The subassembly includes a first substrate that has at least one aperture, a coefficient of thermal expansion (CTE) of eight parts per million per degree Celsius or less, and first and second contacts arranged so as to have a pitch of 200 microns or less. First and second microelectronic elements are respectively electrically connected to the first and second contacts. Wire bonds may be used to connect the second element contacts with the second contacts. A second substrate may underlie either the first or the second microelectronic elements and be electrically interconnected with the first substrate. The second substrate may have terminals configured for electrical connection to a component external to the microelectronic package. A monolithic encapsulant may contact the first and second microelectronic elements and the first and second substrates.

Through interposer wire bond using low CTE interposer with coarse slot apertures

A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer.

Microelectronic assembly with thermally and electrically conductive underfill

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Scotts Valley, CA, United States of America

Simon McElrea