Bell Telephone Laboratories

At&t Bell Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

Simon M Sze

Kwok K Ng

Martin P Lepselter

John M Andrews, Jr

Avid Kamgar

Robert Morgan Ryder

Ernest Labate

Joseph R Ligenza

A new SOI device which permits both the kink effect to be avoided and threshold voltage to be regulated, as well as a new method for fabricating SOI ICs, is disclosed. The new device included an electrically conductive pathway extending from the active volume and terminating in a non-active region of the substrate of the device. A back-gate bias is communicated to, and kink-inducing charges are conducted away from, the active volume through the conductive pathway. The new fabrication methd permits SOI ICs to be fabricated using available circuit designs and pattern delineating apparatus, e.g., IC mask sets. This method involves the formation of a precursor substrate surface which includes islands of insulating material, each of which is encircled by a crystallization seeding area of substantially single crystal semiconductor material. The boundaries of the islands are defined with a first pattern delineating device, e.g., a mask, which, in terms of the pattern it produces, is substantially identical to a second pattern delineating device. The latter device is a component of pattern delineating apparatus used in forming an IC, e.g., an IC mask set, the component being used to delineate the device regions of the IC. A layer of non-single crystal semiconductor material is formed on the precursor substrate surface, and crystallized with little or no displacement of the islands. The pattern delineating apparatus is then used to form an IC in the crystallized material.

Semiconductor-on-insulator (SOI) devices and SOI IC fabrication method

Semiconductor crystal films on a dielectric substrate are advantageously made by a zone melting method. Single-crystal structure is initiated at a seed surface, and made to extend across a dielectric surface by melting and resolidifying. Melting is effected upon irradiation with optical radiation which is focused onto an elongated zone; the zone is moved so as to locally melt successive portions of a layer of precursor material which may be amorphous or polycrystalline. The use of incoherent radiation is convenient, and focusing is typically by using a reflector. The process is conveniently effected under a controlled atmosphere and the layer being crystallized may be encapsulated so that no free semiconductor surface is exposed to an atmosphere.

Method for making semiconductor crystal films

One or more silicon-integrated-circuit chips are attached, active side up, to the top side of a silicon wafer. The top side of the wafer and all but peripheral portions of the attached chip(s) are then coated with an etch-resistant layer. Subsequently, the chips are etched to form sloped edges between the active areas of the chips and the top side of the wafer. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped edges to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. In other embodiments, at least one chip of the type described is attached to each side of a wafer. In such embodiments, connections can also be made through vias in the wafer to selectively interconnect pads and/or terminals included on both sides of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

Packaging microminiature devices

One or more silicon-integrated-circuit chips are attached, active side up, to the bottom side of a silicon wafer. A sloped-wall through-aperture is etched in the wafer in registry with a portion of the active side of each attached chip. A lithographically defined conductive pattern is then formed on the top side of the wafer and on the sloped walls to connect conductive pads on each chip to conductive pads on other chips and/or to conductive terminals disposed along the periphery of the wafer. The resulting packaged chip assembly has advantageous performance and cost characteristics.

In the fabrication of a metal oxide semiconductor field effect transistor (MOSFET) or of a metal gate field effect transistor (MESFET), characterized by a polycrystalline silicon gate (13) and a short channel of about a micron or less, a sequence of steps is used involving the simultaneous formation of source, drain, and gate electrode contacts by a bombardment with a transition metal, such as platinum, which forms metal-silicide layers (19, 21, 18) on the source and drain regions (10.1, 10.2) as well as the silicon gate electrode (13).

Method of making contact electrodes to silicon gate, and source and

A bipolar transistor NPN structure (20) is constructed at a major surface of a silicon body with a P-type polycrystalline silicon electrode (13) contacting a P-type base zone (13.6). Excess acceptor impurities from the polycrystalline silicon electrode (13) are diffused into the base zone (13.6) in order to tailor its conductivity profile.

High speed lateral bipolar transistor

A Schottky barrier contact includes a thin layer of high carrier concentration impurities ion implanted over the contact surface of the semiconductor. This reduces the electronic barrier height, increases the tunneling component, and thus reduces the forward-bias turn-on voltage of the diode. The implanted layer has a carrier concentration at least ten times that of the semiconductor substrate, and a thickness smaller than the width of the inherent depletion region resulting from the internally generated electric field at the metal-semiconductor interface. An implanted layer of the opposite conductivity type raises the barrier height.

Growing community of inventors

New Providence, NJ, United States of America

Simon M Sze