International Business Machines Corporation

Tokyo Electron Limited

Chartered Semiconductor Manufacturing Ltd (corporation)

Samsung Electronics Co., Ltd.

Kabushiki Kaisha Toshiba

Infineon Technologies North America Corp.

Indian Institute of Technology Kanpur

Siddhartha Panda

Richard Stephan Wise

Dureseti Chidambarrao

Huajie Chen

Michael Ray Sievers

Judson Robert Holt

Meikei Ieong

Qiqing Christine Ouyang

Henry K Utomo

Werner A Rausch

Brian L Tessier

Sang-Hyun Oh

Tsutomu Sato

Brian Joseph Greene

Wesley Charles Natzle

David M Dobuzinsky

Yong Meng Lee

Gangadhara Swami Mathad

Rajiv M Ranade

Koichiro Inazawa

Ricky S Amos

Vaidyanathan Balasubramaniam

Rich Wise

Haining S Yang

Haizhou Yin

Kern Rim

Shreesh Narasimha

Lee Chen

Rolf Weis

Thomas W Dyer

Bomy A Chen

Xiao Hu Liu

Rajarao Jammy

Jochen C Beintner

John Christopher Arnold

Yung Fu Chong

Jiang Yan

Nivo Rovedo

Brian L Ji

Sunfei Fang

Hongwen Yan

Arpan Pravin Mahorowala

Ying Li

Wenhe Lin

Rajeev Malik

Chung Woh Lai

Young Way Teh

Brian W Messenger

Oiging C Ouyang

Arpan Mahorawala

JunJung Kim

Srikanteswara Dakshina Murthy

Kamatchi Subramanian

Hakeem Abrar Ahmed

Christophe N Collins

Rie Inazawa

Sang-Hyun c/o Ibm United Kingdom Ltd Oh

Tsutomu Ibm United Kingdom Ltd Sato

Huajie Ibm United Kingdom Ltd Chen

Henry K c/o Ibm United Kingdom Ltd Utomo

Techniques described herein generally relate to methods of manufacturing devices and systems including devices including a substrate with a surface, a conductive polymer film arranged on the surface of the substrate, wherein the conductive polymer film has one or more temperature reactive characteristics, and a pair of electrodes coupled to the polymer film, wherein the pair of electrodes are configured to communicate electrical signals to the conductive polymer film effective to measure the one or more temperature reactive characteristics. The conductive polymer film may be arranged on the surface of the substrate such that a thickness and dopant ratio of the conductive polymer film on the substrate is configurable.

Flexible temperature sensor and sensor array

A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.

Field effect device with reduced thickness gate

A method for etching an organic anti-reflective coating (ARC) layer on a substrate in a plasma processing system comprising: introducing a process gas comprising ammonia (NH), and a passivation gas; forming a plasma from the process gas; and exposing the substrate to the plasma. The process gas can, for example, constitute NHand a hydrocarbon gas such as at least one of CH, CH, CH, CH, CH, CH, CH, CH, CH, CH, CH, CH, CH, CH, and CH. Additionally, the process chemistry can further comprise the addition of helium. The present invention further presents a method for forming a bilayer mask for etching a thin film on a substrate, wherein the method comprises: forming the thin film on the substrate; forming an ARC layer on the thin film; forming a photoresist pattern on the ARC layer; and transferring the photoresist pattern to the ARC layer with an etch process using a process gas comprising ammonia (NH), and a passivation gas.

Method and apparatus for multilayer photoresist dry development

A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.

Method and apparatus for post silicide spacer removal

A method for fabricating the semiconductor structure include a semiconductor substrate having a cross-section hourglass shaped channel region. A stress imparting layer is located adjacent the channel region. The hourglass shape may provide for enhanced vertical tensile stress within the channel region when it is longitudinally compressive stressed by the stress imparting layer.

Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification

A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.

Semiconductor device structure having low and high performance devices of same conductive type on same substrate

A method and apparatus for detecting the endpoint in a dry plasma etching system comprising a first electrode (e.g., upper electrode) and a second electrode (e.g., lower electrode) upon which a substrate rests is described. A direct current (DC) voltage is applied between the first electrode and a ring electrode surrounding the second electrode, and the DC current is monitored to determine the endpoint of the etching process. The DC current is affected by the impedance of the plasma, and therefore responds to many variations including, for example, the plasma density, electron/ion flux to exposed surfaces, the electron temperature, etc.

Method and apparatus for detecting endpoint in a dry etching system by monitoring a superimposed DC current

A semiconductor structure and a method of fabricating the same in which strain enhancement is achieved for both nFET and pFET devices is provided. In particular, the present invention provides at least one spacerless FET for stronger strain enhancement and defect reduction. The at least one spacerless FET can be a pFET, an nFET, or a combination thereof, with spacerless pFETs being particularly preferred since pFETs are generally fabricated to have a greater width than nFETs. The at least one spacerless FET allows to provide a stress inducing liner in closer proximity to the device channel than prior art structures including FETs having spacers. The spacerless FET is achieved without negatively affecting the resistance of the corresponding silicided source/drain diffusion contacts, which do not encroach underneath the spacerless FET.

Method to increase strain enhancement with spacerless FET and dual liner process

A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.

Stressed field effect transistors on hybrid orientation substrate

A method of etching a wafer using resonant infrared energy and a filter to control non-uniformities during plasma etch processing. The filter includes a predetermined array or stacked arrangement of variable transmission regions that mirror the spatial etch distortions caused by the plasma etching process. By spatially attenuating the levels of IR energy that reach the wafer, the filter improves uniformity in the etching process. Filters may be designed to compensate for edge fast etching due to macro-loading, asymmetric pumping in a plasma chamber, and magnetic field cusping.

Method of processing wafers with resonant heating

A field effect transistor ('FET') is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

Structure and method for making strained channel field effect transistor using sacrificial spacer

NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the source and the drain of the PMOS device is epitaxially grown of a material which causes a shift in the strain of the PMOS device channel in the compressive direction.

Strained MOS devices using source/drain epitaxy

Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.

Method to engineer etch profiles in Si substrate for advanced semiconductor devices

A plasma etching system having a wafer chuck with a magnet that applies a magnetic field over a wafer to shield the wafer from charged particles. The magnetic field is parallel with the wafer, and is strongest near the wafer surface. The magnetic field may be straight, or circular. In operation, electrons are deflected from the wafer by the Lorentz force, the wafer acquires a positive charge, and ions are deflected by electrostatic repulsion. Neutral species are allowed through the magnetic field, and they collide with the wafer. Neutral species generally provide more isotropic and material-selective etching than charged particles, so the present magnetic field tends to increase etch isotropy and material selectivity. Also, the magnetic field can protect the wafer from seasoning processes designed to clean unwanted films from the chamber surface as seasoning processes typically rely on etching by charged particles.

Apparatus and method for shielding a wafer from charged particles during plasma etching

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Beacon, NY, United States of America

Siddhartha Panda