International Business Machines Corporation

Applied Materials, Inc.

Globalfoundries Inc.

Freescale Semiconductor,inc.

Globalfoundries U.S. 2 LLC

Siddarth A Krishnan

Unoh Kwon

Michael Patrick Chudzik

Vijay Narayanan

Ruqiang Bao

Takashi Ando

Shahab Siddiqui

Keith Kwong Hon Wong

Rishikesh Krishnan

Naim Moumen

Lan Yu

Jeffrey W Sleight

Ravikumar Ramachandran

Paul F Ma

Dechao Guo

Hemanth Jagannathan

Carl John Radens

Ramachandra Divakaruni

Seshadri Ganguli

Wesley Charles Natzle

Christophe J Chevallier

Oleg Gluschenkov

Ludovic Godet

Richard Stephan Wise

Yixiong Yang

William K Henson

Joseph Francis Shepard, Jr

Hongwen Yan

Shreesh Narasimha

Andrew Herbert Simon

Huiming Bu

Vamsi Krishna Paruchuri

Dae-Gyu Park

Paul Christian Parries

Xing Chen

Naomi Yoshida

Nicolas L Breil

Srinivas Gandikota

Martin Michael Frank

Zhengwen O Li

Ramachandran Muralidhar

Shashank Sharma

Eduard Albert Cartier

Renee Tong Mo

Jinping Liu

Rutger Meyer Timmerman Thijssen

Roger Allan Quon

Michael P Belyansky

Yu Lei

Mingwei Zhu

Balaji Kannan

Deepak Kamalanathan

Min Dai

Tyler Sherwood

Archana Kumar

Rashmi Jha

Rekha Rajaram

Maryjane Brodsky

Fuxi Cai

Oh-Jung Kwon

Wei V Tang

Federico Nardi

Shih Chung Chen

Atashi Basu

Rajesh Sathiyanarayanan

Joyeeta Nag

Lin Dong

Charlotte DeWan Adams

Murshed Mahmud Chowdhury

Wenyu Zhang

Bachir Dirahoui

Shishir K Ray

Nicolas Louis Gabriel Breil

Wei He

Ria Someshwar

Amirhasan Nourbakhsh

Sang Ho Yu

Yanfeng Wang

Yue Liang

Jacqueline S Wrench

Steven C H Hung

Xi Li

Yi Xu

Ricardo Alves Donaton

Liqi Wu

James Kenyon Schaeffer, Iii

El Mehdi Bazizi

Kai Zhao

Aritra Dasgupta

Domingo A Ferrer

Kriteshwar Kaur Kohli

Andreas Kerber

Naamah Argaman

Chi-Chou Lin

Ashish Pal

Joseph F Salfelder

Byunghoon Yoon

Sage Toko Garrett Doshay

Kai Ng

Ki Cheol Ahn

Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.

Dual oxide analog switch for neuromorphic switching

Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.

Methods of forming semiconductor structures

A method of correcting bias temperature instability in memory arrays may include applying a first bias to a memory cell, where the memory cell may include a memory element and a select element, and the first bias may causes a value to be stored in the memory element. The first bias causes a bias temperature instability (BTI) associated with the memory cell to increase. The method may also include applying a second bias to the memory cell, where the second bias may have a polarity that is opposite of the first bias, and the value stored in the memory element remains in the memory element after the second bias is applied. The second bias may also cause the BTI associated with the memory cell to decrease while maintaining any value stored in the memory cell.

Bias temperature instability correction in memory arrays

Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.

Edge protection on semiconductor substrates

A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.

Soft reset for multi-level programming of memory cells in non-von neumann architectures

Exemplary semiconductor processing methods may include forming a p-type silicon-containing material on a substrate including a first n-type silicon-containing material defining one or more features. The p-type silicon-containing material may extend along at least a portion of the one or more features defined in the first n-type silicon-containing material. The methods may include removing a portion of the p-type silicon-containing material. The portion of the p-type silicon-containing material may be removed from a bottom of the one or more features. The methods may include providing a silicon-containing material. The methods may include depositing a second n-type silicon-containing material on the substrate. The second n-type silicon-containing material may fill the one or more features formed in the first n-type silicon-containing material and may separate regions of remaining p-type silicon-containing material.

Power device structures and methods of making

Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 &#x3bc;m. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.

Graded doping in power devices

Exemplary methods of forming a semiconductor structure may include forming a layer of metal on a semiconductor substrate. The layer of metal may extend along a first surface of the semiconductor substrate. The semiconductor substrate may be or include silicon. The methods may include performing an anneal to produce a metal silicide. The methods may include implanting ions in the metal silicide to increase a barrier height over 0.65 V.

Methods of forming doped silicide power devices

Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.

Deep trench integration processes and devices

Exemplary methods of forming a memory structure may include forming a layer of a transition-metal-and-oxygen-containing material overlying a substrate. The substrate may include a first electrode material. The methods may include annealing the transition-metal-and-oxygen-containing material at a temperature greater than or about 500&#xb0; C. The annealing may occur for a time period less than or about one second. The methods may also include, subsequent the annealing, forming a layer of a second electrode material over the transition-metal-and-oxygen-containing material.

Annealing processes for memory devices

A method of setting multi-state memory elements into at least one low-power state may include receiving a command to cause a memory element to transition into one of three or more states; applying a first signal to the memory element to transition the memory element into the one of the three or more states, where the three or more states are evenly spaced in a portion of an operating range of the memory element; receiving a command to cause a memory element to transition into a low-power state; applying a second signal to the memory element to transition the memory element into the low-power state, where the low-power state is outside of the portion of the operating range of the memory element by an amount greater than a space between each of the three or more states.

Non-uniform state spacing in multi-state memory element for low-power operation

Methods of modifying the threshold voltage of metal oxide stacks are discussed. These methods utilize materials which provide larger shifts in threshold voltage while also being annealed at lower temperatures.

Methods and materials for modifying the threshold voltage of metal oxide stacks

Soft reset for multi-level programming of memory cells in non-Von Neumann architectures

Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack includes a bottom layer and a middle layer formed over the at least one semiconductor fin in the first region. A second work function stack includes a first layer and a second layer formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack, but has a smaller thickness than the middle layer.

Shared metal gate stack with tunable work function

Growing community of inventors

Peekskill, NY, United States of America

Siddarth A Krishnan